Timeline for How Are RAM Memory Addresses Determined
Current License: CC BY-SA 4.0
13 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 28, 2021 at 14:28 | audit | First posts | |||
| Apr 28, 2021 at 14:28 | |||||
| Apr 25, 2021 at 9:06 | history | edited | pjc50 | CC BY-SA 4.0 |
deleted 6 characters in body
|
| Apr 24, 2021 at 18:26 | comment | added | Criticizing Israel not allowed | @jdow Inside a RAM chip is columns and rows and also banks, but from a programming point of view it doesn't matter, you can just imagine it as 1 column and 1 bank and 65536 rows (if it's 16 bit for example). | |
| Apr 24, 2021 at 10:59 | comment | added | pjc50 | @jdow Yes, as Rodney says there are rows/columns inside DRAM chips. Memory mapped IO is indeed using the word "mapped" in the same sense; the CPU makes a read/write request on the memory bus, but it gets routed to something that isn't memory, or is inside a peripheral. | |
| Apr 24, 2021 at 8:02 | comment | added | Rodney | Actually DRAM chips do have rows, columns and banks (hence the need for the RAS, CAS and bank-select signals). The memory controller logic deals with this, it is abstracted from the CPU. | |
| Apr 24, 2021 at 4:16 | comment | added | Ken Shirriff | The answer discusses a "multiplexer", but I think that should be "decoder/demultiplexer". | |
| Apr 23, 2021 at 22:02 | comment | added | Hellion | @jdow There's no "column/Row" to be considered. Logically, each RAM chip consists of a series of bytes, numbered sequentially starting at 0. The full address represents "which chip is this byte stored on, and where in the chip is it stored?". For a 12-bit address, you have 16 chips with 256 bytes each; the top 4 bits can be the chip and the lower 8 bits are the address; so address 0x123 means "look on chip 0x1, in address 0x23." If I swap a different chip (of the same type and size) into my motherboard, the new chip still has its bytes numbered sequentially starting at 0. | |
| Apr 23, 2021 at 21:18 | comment | added | jdow | Wait, so the address represents the column/row of where the data is stored in RAM, right? So if it was an 8 bit address the 4 bits would be for the column and 4 for the row? So for the address 0xFF0000 that would a 3 byte address. Which once decoded by the multiplexer, addresses the 4080 column/row and the 0 column/row? | |
| Apr 23, 2021 at 20:07 | comment | added | jdow | Thank you for clearing that up. It helps to make a lot more sense of things. So if the CPU was requiring data, it would send a read request to the memory controller, right? If so is that what mapping is, or is it something else similar to memory mapped I/O? | |
| Apr 23, 2021 at 19:57 | comment | added | pjc50 | The BIOS is in the memory map - but as a ROM (read only memory). So yes, executing the BIOS is done through the CPU's memory interface. The controller doesn't create the addresses, it maps them - ie it defines what happens when a particular address is accessed. | |
| Apr 23, 2021 at 19:39 | comment | added | jdow | Thank you for the answer. I have to confess, I'm not good with the electronics side. I do understand when you say the chips don't have an absolute address. I believe the memory controller has a part to play in creating the addresses, but I'm not entirely sure how. Also, you spoke about a sort of scan occurring when the BIOS is loaded, but my understanding is that the memory has already been addressed before the BIOS loads, I could be very wrong though. | |
| Apr 23, 2021 at 15:23 | history | edited | pjc50 | CC BY-SA 4.0 |
added 767 characters in body
|
| Apr 23, 2021 at 15:17 | history | answered | pjc50 | CC BY-SA 4.0 |