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I learnt some about pipelining but those were 4-stage and 5-stage and I think that modern pipelining typical is much longer and more complicated in practice. How long are typical pipelines and how much can we expect them to increase and where is the point of reaching diminshing returns in performance gains for longer pipelines?

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    I think you can expect them to be in the 20's but my memory is rusty – aaronman Sep 8 '13 at 2:17
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Intel had 5 pipeline stages in its original Pentium architecture. The number of stages peaked at 31 in the Prescott family, but decreased after that. Today, in the Core series II processors (i3, i5, and i7), there are 14 stages in the processor pipeline.

Microarchitecture   Pipeline stages
P5 (Pentium)             5
P6 (Pentium 3)          10
P6 (Pentium Pro)        14
NetBurst (Willamette)   20
NetBurst (Northwood)    20
NetBurst (Prescott)     31
NetBurst (Cedar Mill)   31
Core                    14
Bonnell                 16
Sandy Bridge            14
Silvermont              14 to 17
Haswell                 14
Skylake                 14
Kabylake                14

Prescott achieved only modest gains in performance over its predecessor, and its more complex design demanded substantially more power relative to its performance gains. Although there were other contributing factors to Prescott's disappointing performance, it seems clear that increasing the number of pipelining stages eventually achieves diminishing returns.

References
Prescott Pushes Pipelining Limits
The Intel Architecture Processor Pipeline
List of Intel CPU Microarchitectures
The Optimum Pipeline Depth for a Microprocessor

  • Any update for the last 4 years? – toasted_flakes Jan 16 '17 at 22:17
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    @toasted_flakes: After Bonnell, Intel more or less settled on 14 pipeline stages (16 with Fetch/Retire). See List of Intel CPU Microarchitectures. – Robert Harvey Jan 16 '17 at 22:32
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    A Skylake processor also has a 224 entry queue for out-of-order execution of instructions, plus a queue for up to 72 outstanding loads, plus a 97 entry scheduler queue, so the delay from an instruction being read to the instruction being retired can be enormous, say if you have hundred dependent load instructions, followed by a few hundred dependent divide instructions. But that doesn't give you the disadvantages that too many pipeline stages have. – gnasher729 Jan 17 '17 at 0:37
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Regarding other modern processors:

  • ARM up to 7: 3 stages (still widely used is simpler devices)
  • ARM 8-9: 5 stages;
  • ARM 11: 8 stages;
  • Cortex A7: 8-10 stages;
  • Cortex A8: 13 stages;
  • Cortex A15: 15-25 stages.

From Wikipedia.

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