Well, the title is pretty much self explanatory, but I'll expound it a bit, and say the origin of my question.

So, I've been wondering as to how the CPU knows when it received the RAM. I'm pretty sure it doesn't OR the RAM outputs together, because 0x00 is still a number, yet ORing that together says that the RAM has not outputed anything. Does the RAM have some kind of "request acknowledged" line? Well, my friend was making an MC CPU, and he used interrupts for RAM reading, so that's where I got this idea.

Anyways, the origin of my problem is probably when I was thinking about Virtual Memory. In virtual memory, you have to fetch from the disk and to the RAM. How does one compensate for the gap between the speeds? May this be answered too?

  • 1
    What have you searched for? How (most/common/modern) computers work is well known and documented.
    – Telastyn
    Commented Nov 17, 2013 at 2:07
  • Telastyn: I truthfully haven't done that yet, but my statement is so English-ish that searching it wouldn't result in anything good.
    – Myrl
    Commented Nov 17, 2013 at 2:12
  • 1
    It's not entirely clear what you're asking. Are you trying to understand how the memory bus works, or are you trying to understand how virtual memory works? (These are different questions dealing with two different parts of the system.)
    – greyfade
    Commented Nov 17, 2013 at 2:29
  • @greyfade I'm actually asking for both. I want to understand how the memory bus works and how the CPU can compensate for the different speeds.
    – Myrl
    Commented Nov 17, 2013 at 2:40

1 Answer 1


Yes, there is a Data Acknowledge signal. It asserts that the data has been placed onto the memory bus, and is available to the processor for reading.

Briefly, the memory read cycle works like this:

  1. The processor initiates a read bus cycle by floating the address of the memory location on the address lines.
  2. Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
  3. The processor then sets the Read/Write signal to high, i.e. read.
  4. Now the processor asserts the data strobe signal. This signals to the memory that the processor is ready to read data.
  5. The memory subsystem decodes the address and places the data on the data lines.
  6. The memory subsystem then asserts the data acknowledge signal. This signals to the processor that valid data can now be latched in.
  7. The processor latches in the data and negates the data strobe. This signals to the memory that the data has been latched by the processor. The processor also negates the address strobe signal.
  8. Memory subsystem now negates the data acknowledgement signal. This signals the end of the read bus cycle.

The Data Acknowledge signal is asserted in Step 6.

Processors compensate for the amount of time it takes to read memory by imposing Wait States. However, virtual memory is an operating system function, so the operating system manages the time it takes to read the data off the hard disk and swap it into memory, where the CPU can read it in the usual way.

In simple terms, the CPU simply waits in a loop until the data is available.

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    Be aware this is one specific, all be it the most common case of accessing the contents of RAM. In some cases the RAM is expected to have the correct data on the bus by the next (half or full) clock cycle.
    – mattnz
    Commented Nov 17, 2013 at 4:31
  • regarding point#2, how does the cpu validate that the address lines are stable ? does it just wait for some specified number of clock cycles ? or how Commented Dec 4, 2022 at 14:40

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