I know that in 32bit machine, cpu read from memory 32bits at a time. since the registers in this case is 32bit in size too, I can understand how this works.

What I don't understand is how the cpu implement load instructions of 1 byte. does it load the whole word where the single byte is located to the register, then perform some kind of "byte shifting", or does the cpu can load a single byte, in this case when does the byte masking happen, is it until the byte got loaded in the register, or it happen when byte is send through the data bus ?

P.S. The cpu Im using is MIPS, the instructions Im talking about are: lb or lbu

  • @JohnGaughan the documentation doesn't include implementation of this instructions. And Im interested in single byte reading in general not necessarily MIPS cpu.
    – AlexDan
    Apr 28, 2014 at 17:21
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    @gnat that doesn't answer my question at all, that's totally a different question.
    – AlexDan
    Apr 28, 2014 at 17:24
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    I am not sure this question can be answered anyway. What goes on in microcode (below machine code) is vendor-specific and not often documented in great depth. I would expect something like MIPS would be better documented given its age and that it is used in academia to teach this stuff (in fact my current Master's program used MIPS to teach architecture). But if the MIPS documentation does not say specifically, then you may be out of luck.
    – user22815
    Apr 28, 2014 at 17:27
  • in short my question is: can a 32bit cpu read a single byte from memory? if yes, how does it accomplish this task? I know that the implementation differ from one cpu to another, so Im looking for any possible implementation
    – AlexDan
    Apr 28, 2014 at 17:34

3 Answers 3


It depends.

Some (CISC) CPUs have byte-wise loads that can address individual bytes so the byte of interest is the low-order 8-bits on the bus; the rest of the bits are masked off.

Many RISC CPUs will do word-load, barrel shift, while others will do word-load, bit shift and in the middle, are ones that do word-load, byte shift.

Some CPUs will do consecutive word-loads when a two-byte value spans a 32-bit boundary, shifting and masking the words together.

CPU families may do different implementations depending on the particular processor model. That explains why there is no description of the implementation; it's a decision only the vendor cares about.

As for performance, you will just have to test it on the particular CPU and memory configurations you care about.

  • For uncacheable loads from a memory-mapped I/O register, widening a MIPS lbu instruction to a 32-bit load would not be allowed. Reading the adjacent I/O registers in the containing word could have side-effects, so CPUs with MMIO (like MIPS) need to truly support byte loads and especially byte stores. (Unless lbu was documented to actually read the whole containing word, but it isn't.) Since CPUs need to support byte loads / stores for MMIO, they use the same hardware for memory. See this Q&A for more about byte loads/stores on modern CPUs. May 28, 2018 at 2:05
  • Grabbing the containing word from cache and then extracting the relevant byte might be more or less what happens for cached loads, but byte stores can't really be implemented as a read-modify-write unless it's an atomic RMW, otherwise that could have observable side-effects. (Again, see the Q&A linked in the previous question). It's basically a myth that RISC CPUs can't deal with separate bytes. Only early DEC Alpha was like that (literally no load-byte / store-byte instructions). May 28, 2018 at 2:10

In many 32-bit machines without a memory cache, the memory will be divided into four 8-bit-wide sections, each of which will be connected to eight bits of the system bus and will have its own "enable" logic. If a processor executes a 16-bit store instruction, it will enable two of the eight sections and output the appropriate data on the wires that connect to them. The other two sections won't be enabled, so their contents won't be affected.

Note that while some machines split up both write and read operations the same way, it's really only necessary that the memory subsystem allow "partial" writes. If the processor performs a 16-bit load, it will expect to receive data from the two 8-bit sections that contain the address in question, but won't care if the other sections supply data as well. Each section has its own separate set of eight data pins, and the processor would ignore whatever data was placed on the unused sets.

Note also that in systems with memory caches, things get more complicated. Depending upon the caching architecture, a 16-bit store might cause the two memory banks that are being written to be set for "write" while those which aren't would be set for "read"; all 32 bits of the cache would then be set to "write" (16 bits would grab data being stored by the CPU, while the other 16 would grab the other half of that same word, fetched from memory). Alternatively, it might only write 16 bits to the cache, but set flags indicating that the other 16 bits of that word are "unknown". Despite this complexity, most CPU designers believe the semantic cleanliness of allowing 8- and 16-bit "store" instructions is worth the cost.


CPU can read single byte, but not only that one byte. In broader term, the byte might not be in memory yet, so a page needed to be loaded, update memory map and a store a chunk in cache (cache is in CPU too), then it can be loaded.

If you need less than a word, sign extension might be performed as mentioned in MIPS instruction set. The cpu loads the machine word (32bit) and depending on the instruction it'll either perform sign extension or nullify the uninteresting bytes. So, it's not simply "byte shifting". Operations are done on register, so after it's loaded.

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