In many 32-bit machines without a memory cache, the memory will be divided into four 8-bit-wide sections, each of which will be connected to eight bits of the system bus and will have its own "enable" logic. If a processor executes a 16-bit store instruction, it will enable two of the eight sections and output the appropriate data on the wires that connect to them. The other two sections won't be enabled, so their contents won't be affected.
Note that while some machines split up both write and read operations the same way, it's really only necessary that the memory subsystem allow "partial" writes. If the processor performs a 16-bit load, it will expect to receive data from the two 8-bit sections that contain the address in question, but won't care if the other sections supply data as well. Each section has its own separate set of eight data pins, and the processor would ignore whatever data was placed on the unused sets.
Note also that in systems with memory caches, things get more complicated. Depending upon the caching architecture, a 16-bit store might cause the two memory banks that are being written to be set for "write" while those which aren't would be set for "read"; all 32 bits of the cache would then be set to "write" (16 bits would grab data being stored by the CPU, while the other 16 would grab the other half of that same word, fetched from memory). Alternatively, it might only write 16 bits to the cache, but set flags indicating that the other 16 bits of that word are "unknown". Despite this complexity, most CPU designers believe the semantic cleanliness of allowing 8- and 16-bit "store" instructions is worth the cost.