From Instruction pipelining section in Tanenbaum's Structured Computer Organization:
Pipelining allows a trade-off between latency (how long it takes to execute an instruction), and processor bandwidth (how many MIPS the CPU has).
With a cycle time of T nsec, and n stages in the pipeline, the latency is nT nsec because each instruction passes through n stages, each of which takes T nsec.
Since one instruction completes every clock cycle and there are 10^9/T clock cycles/second, the number of instructions executed per second is 10^9/T. To get the number of MIPS, we have to divide the instruction execution rate by 1 million to get (10^9/T)/10^6 = 1000/T MIPS.
I think the smaller latency the better, and the bigger bandwidth the better. Since the two are related as reciprocals, they always move simultaneously in either both good or both bad directions. Then how do the two form tradeoff? Thanks.