Is it correct that:
a microinstruction is what can be executed directly on hardware?
an instruction in ISA either can run on hardware (in this case, the instruction is a microinstruction?), or must be interpreted by a microprogram to be a sequence of microinstructions to run on hardware?
From Tanenbaum's Structured Computer Organization, are "instructions", "register-memory instructions" and "register-register instructions" mentioned in the following quote microinstructions or instructions in ISA?
Most instructions can be divided into one of two categories: register-memory or register-register.
Register-memory instructions allow memory words to be fetched into registers, where, for example, they can be used as ALU inputs in subsequent instructions. (‘‘Words’’ are the units of data moved between memory and registers. A word might be an integer. We will discuss memory organization later in this chapter.) Other register-memory instructions allow registers to be stored back into memory.
A typical register-register instruction fetches two operands from the registers, brings them to the ALU input registers, performs some operation on them (such as addition or Boolean AND), and stores the result back in one of the registers. The process of running two operands through the ALU and storing the result is called the data path cycle and is the heart of most CPUs. To a considerable extent, it defines what the machine can do. Modern computers have multiple ALUs operating in parallel and specialized for different functions. The faster the data path cycle is, the faster the machine runs.
Is the "instruction" in a fetch-decode-execute cycle mentioned in the following quote a microinstruction or an instruction in ISA?
If "instruction" means a microinstruction, what is a "cycle" for an instruction in ISA when it needs to be interpreted by a microprogram?
When running a register-memory instruction (as in part 2) to fetch memory words into registers, does it call itself to fetch itself from memory into the instruction register in step 1?
The CPU executes each instruction in a series of small steps. Roughly speaking, the steps are as follows:
- Fetch the next instruction from memory into the instruction register.
- Change the program counter to point to the following instruction.
- Determine the type of instruction just fetched.
- If the instruction uses a word in memory, determine where it is.
- Fetch the word, if needed, into a CPU register.
- Execute the instruction.
- Go to step 1 to begin executing the following instruction.
This sequence of steps is frequently referred to as the fetch-decode-execute cycle.
When talking about RISC or CISC, are they referring to microinstructions, or instructions in ISA? Thanks.
I agree with your interpretation. And if an ISA instruction ties to a single microinstruction, I would still call the instruction an instruction and the microinstruction a microinstruction, even knowing that there's a 1:1 tie. There are all sorts of chip architectures, but I imagine that internally there are differences in naming and things are kept separate that way, e.g. a chip designer might say something like "the MOV instruction implementation consists solely of invocation of the _mov microinstruction". I'm making up my own naming convention here; the point is that there are still two different entities here, even if they happen to correspond 1:1.
Those operations would be instructions; whether they are implemented as single microinstructions or as microprograms, they are still conceptually instructions.
Those operations would also be instructions; the CPU will never have to "fetch" a microinstruction. It already has the correct microinstructions necessary for any given instruction it fetches burned into its circuit design.
In a pure RISC architecture, there is no instruction / microinstruction distinction. Each instruction is basically a single microinstruction, although the term "microinstruction" would not typically by used (since it's not necessary to draw such a distinction). When talking about a CISC device, I'd imagine that people would talk mostly about instructions; if they're referring to the internal microinstructions (which are less likely to be a topic of everyday discussion, in my experience), then people will explicitly say "microinstruction".
1) An Instruction Set Architecture defines the interface that is used to program a processor. Note that this does not define the implementation. When a CPU designer goes about designing the processor, they may implement this ISA in various different ways. In fact, the various Intel processors have each implemented the x86 ISA in many different ways over the years.
Computer architecture is generally delineated around an ISA. Computer microarchitecture is very specific to a particular processor. For example, a Pentium vs. a Pentium Pro implement for the most part the exact same instruction set, i.e. the x86 ISA. But their microarchitectures were drastically different. (The Pro was out of order for example).
One of the methods often used to get pipelines to be very fast is to reduce the more complex instructions to microinstructions. These are used by the "back-end" of the processor, which is the part that has one or more execution units.
Therefore, the point of the two types of instructions ISA instruction vs. microinstruction has to do with whether you are discussing the ISA, i.e. the interface, or the microarchitecture, i.e. the implementation.
2) As far as your second question, Tanenbaum was almost certainly talking about ISA level instructions because his books are about computer architecture. Microarchitecture is much more hardware designer centric. See John Stokes, "Inside the Machine" if you are interested in microarchitecture.
3) For most real processors, fetch-decode-execute is entirely too simplistic to describe what really goes on inside. However, from an ISA point of view, it defines a good abstraction to the steps an instruction takes.
The instruction fetch is done by dedicated hardware, so it is different from the load instruction data fetch. Usually there are actually two bus masters, instruction and data. These buses often have their own caches. In some cases, i.e. harvard architectures, the data and instruction memory maps are entirely separate.
4) RISC vs. CISC is entirely regarding the ISA, i.e. the interface. However, the RISC mindset of using a reduced instruction set is very much to simplify the microarchitecture. The effect is that the microarchitectural instructions are generally exactly the same as the ISA instructions in RISC processors.