I am having a hard time finding documentation that explains precisely how the various TLB caches are used in modern processors. Most modern processors have separate TLBs for code/data. That in itself is fairly obvious since we know the type from the instruction that initiates the query. However, most modern processors also have separate TLBs for different page sizes. How does the CPU know in which to look up for a particular virtual address?

From what I could gather, some Power processors offer a way to partition the address space with regions dedicated to certain page sizes (either hardcoded in the chip or presumably tweakable from a dedicated register). More recent AMD/Intel x64 processors do not appear to mention anything like this.

Does the CPU perform the lookup in all (4kb/2mb/1gb) TLBs in parallel? How would this work with L1/L2 TLBs? Is the TLB not associating the input virtual address to the final translation result and instead storing results from the Page Directory Entries/Page Table Entries/etc (which would be segmented in page size already)? Some Power processors have an ERAT cache for the input virtual address -> final translated physical address + protection attributes which seems to hint that the TLB stores PDE/PTE. Could someone elaborate a bit on this?

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After several hours of research I was able to find the following information:

Newer intel/amd processors that have separate TLBs per page size will lookup in both at the same time in hope that one will hit. When an L2 TLB cache is present, it will be searched afterwards before finally attempting a page table walk.

Older Power processors and ARM processors have a single TLB with mixed page sizes. This implies multiple comparisons in case of overlap.

Some processors have a cache above the TLB with fewer supported page granularities (ERAT for Power and microTLB for ARM).

Some processors have an internal page walking cache (ARM) to cache intermediate page walking data.

In all processors, the TLB stores the virtual address tag used for the lookup, the physical frame number and access information (r/w/e) and possibly a process ID and VM ID or similar to avoid invalidating the TLB on process/VM context switch.

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