I am having a hard time finding documentation that explains precisely how the various TLB caches are used in modern processors. Most modern processors have separate TLBs for code/data. That in itself is fairly obvious since we know the type from the instruction that initiates the query. However, most modern processors also have separate TLBs for different page sizes. How does the CPU know in which to look up for a particular virtual address?
From what I could gather, some Power processors offer a way to partition the address space with regions dedicated to certain page sizes (either hardcoded in the chip or presumably tweakable from a dedicated register). More recent AMD/Intel x64 processors do not appear to mention anything like this.
Does the CPU perform the lookup in all (4kb/2mb/1gb) TLBs in parallel? How would this work with L1/L2 TLBs? Is the TLB not associating the input virtual address to the final translation result and instead storing results from the Page Directory Entries/Page Table Entries/etc (which would be segmented in page size already)? Some Power processors have an ERAT cache for the input virtual address -> final translated physical address + protection attributes which seems to hint that the TLB stores PDE/PTE. Could someone elaborate a bit on this?