First and foremost when you say "typically" I would have to disagree with that. Yes, in text books all derived from each other they talk about those states in the pipeline. But that was a long time ago now and pipelines have changed in size and shape every generation (every year or two). But that is not relevant to your question.
The answer is "it depends" it is up to the folks designing the particular core as to what they want to do. For simple logical operations, and, or, not, etc. Would really need to justify why they need more than one. Perhaps two if they argue flag comparisons needed another, possible but very unlikely. Fixed point addition, unless the operands are so wide to not close timing for the target clock rate then they shouldnt need more than one clock. For multiply or divide though, the amount of logic required to take N bit operands from N-ish numbers of clocks to one goes up exponentially, so if they have a multiply or divide at all, and if they choose to make it one clock there is a real tradeoff, and they may still run into timing closure for a target clock rate. They could choose to deal with yield and cost per unit or allow two clocks for example and increase their margin.
In short, there are no absolute answers, no typical pipe designs, no general assumptions about how many clocks things take since the advent of a pipeline. Bitwise logical and addition/subtraction instructions should be one clock, but others may be more than one but may be hidden in the pipe and just feel the same anyway (the entire point of a pipeline).