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Typically for a single instrcution, 6 machine cycles are needed:

  1. FETCH instruction
  2. DECODE instruction
  3. EVALUATE ADDRESS
  4. fetch OPERANDS
  5. EXECUTE oepration
  6. STORE result

My concern is regarding the fifth step; excute operation. This is done in the ALU which is simply somehow a group of digital circuits which do ADD, MUL, XADD, ...etc.

My question: Is the time taken (in terms of clock cycles) to excute an ADD for example, equal to that taken to excute XADD? I mean are the digital circuits for each individual operation designed in a way to consume the same number of clock cycles?

In other words, is the machine cylce time fixed?

  • BTW, I found some info in this books.google.de/…, but it doesn't help. Just saying in case anyone want to refer to. – AhmedWas Mar 4 '16 at 8:45
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    It all depends on the processor. On some, a complicated instruction may take several clock cycles to complete. – Simon B Mar 4 '16 at 9:01
  • @SimonB: Indeed. The VAX-11 actually had an FPD (first part done) bit in the flags register to indicate that a long-running instruction (e.g., POLY, which evaluates a polynomial) had been interrupted and the instruction should not simply be restarted. – TMN Mar 4 '16 at 14:49
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    An extreme case would be something like the Z80 instruction LDIR (or LDDR), which implements an entire data copy loop in one instruction. The number of cycles this will take depends on the data that it is asked to copy. – Simon B Mar 4 '16 at 15:31
  • @SimonB Or, indeed, the X86 equivalent "REP MOVSB" (note that the Z80 was an enhanced version of the Intel 8080, as was the 8086, so there's a lot of overlap). – Jules Mar 6 '16 at 19:12
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In most cases, yes, cycle time for each stage is fixed. There are some exceptions, depending on processor. But the description you give is vastly over-simplified. Modern processors are organised in pipelines, so that one stage of execution of one instruction can occur at the same time as others. While some processors use a 6-stage pipeline like you describe, they are a small minority. Most modern processors split the operation into many more stages, each of which takes once cycle. For example, Intel Core processors of the current generation have 19 stages, each of which takes a single cycle. In some circumstances an instruction may skip one of them. Usually, multiple instructions are executed in different stages simultaneously, but some instructions in some circumstances will prevent other operations progressing (e.g. branch mispredictions, or if no instructions are ready because they need to wait for data that has not been produced yet). Also, the processor core may have multiple pipelines so multiple instructions run completely in parallel, and in some architectures not all pipelines are capable of execution of all instruction types. Instruction fetch and decoding is shared between all pipelines, and in many cases can handle many instructions per cycle. In modern processors based on CISC instructions like Intel x86 the instructions are translated into RISC-like micro instructions before execution, so one program instruction may translate to multiple instructions in the pipeline (or vice versa). Determining the actual performance in real world situations is extremely difficult.

  • Thanks for the answer. Disagree with "Instruction fetch and decoding is shared between all pipelines", as each pipline takes one instruction and another pipline takes next instruciton and so on. But the individual stages for each instruction are NOT shared. – AhmedWas Mar 4 '16 at 9:07
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    Fetch and decoding operates on multiple instructions in a batch, typically, so pipelines cannot pick and choose a single instruction to fetch or decode. A single fetch operation will work on a full cache line, which may produce as many as 16 external instructions and potentially even more micro instructions. These then need to be distributed to pipelines, which can't be done until they're decoded because the dependencies between them and the available operations on different pipelines are relevant for making that decision. – Jules Mar 4 '16 at 9:10
  • Thanks again :) Kindly merge this comment in your answer. I think it's needed to make the whole thing clearer. – AhmedWas Mar 4 '16 at 9:34
  • My two cents concerning terminology (please let me know if I'm wrong): (1) execution unit refers to one ALU unit (slice) that can execute certain types of ALU operations (or part thereof) independent of another execution unit. For example, an execution unit may be able to perform logical-and, logical-or, logical-xor, logical-not, addition, subtraction. A CPU core may have one or more execution units. (2) processing element is what we commonly refer to as "cores", having an instruction pointer (program counter) and a register file (or something equivalent). – rwong Mar 6 '16 at 23:09
  • (3) pipeline refers to the fact that machine code undergoes several stages in the CPU core, in order to be executed. (4) In this question, the XADD does not appear to be a RISC instruction, since it involves a memory load, arithmetic, and a memory store - all inside a single instruction. This does not sound like RISC. – rwong Mar 6 '16 at 23:11
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First and foremost when you say "typically" I would have to disagree with that. Yes, in text books all derived from each other they talk about those states in the pipeline. But that was a long time ago now and pipelines have changed in size and shape every generation (every year or two). But that is not relevant to your question.

The answer is "it depends" it is up to the folks designing the particular core as to what they want to do. For simple logical operations, and, or, not, etc. Would really need to justify why they need more than one. Perhaps two if they argue flag comparisons needed another, possible but very unlikely. Fixed point addition, unless the operands are so wide to not close timing for the target clock rate then they shouldnt need more than one clock. For multiply or divide though, the amount of logic required to take N bit operands from N-ish numbers of clocks to one goes up exponentially, so if they have a multiply or divide at all, and if they choose to make it one clock there is a real tradeoff, and they may still run into timing closure for a target clock rate. They could choose to deal with yield and cost per unit or allow two clocks for example and increase their margin.

In short, there are no absolute answers, no typical pipe designs, no general assumptions about how many clocks things take since the advent of a pipeline. Bitwise logical and addition/subtraction instructions should be one clock, but others may be more than one but may be hidden in the pipe and just feel the same anyway (the entire point of a pipeline).

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Let's ignore that your model is not how a typical modern CPU works; it was quite reasonable a few years ago.

On a modern CPU, the clock rate is not absolutely fixed, but it definitely doesn't change from instruction to instruction. The CPU will measure its temperature, or will be told by the operating system that it needs to use as little power as possible, and as a result can change its clock speed over some considerable time (many milliseconds). So the clock rate can be reduced to reduce the amount of heat produced or to reduce the power consumption (the voltage will be reduced, which makes everything run slower, but saves huge amounts of power).

Each individual operation in the CPU will be limited to exactly one cycle. It has to finish in that one cycle. Things that don't work in a single cycle are split into more operations which each take a single cycle. If xadd takes more picoseconds than add, then the CPU designers have two choices: Make a clock cycle longer so that xadd can execute in one cycle (making add slower than it needs to be), or making the clock cycle shorter, just long enough for add, and split the xadd instruction into two units of work that each take one cycle. That choice of clock cycle length applies to everything.

You might google for a diagram of the microarchitecture of a newer Intel CPU. It may come as a shock to the system :-)

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