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Given a modern 64-bit architecture with 6-bytes used for each page pointer, 1 MB pages, and 16 GB installed memory:

a) How would I calculate how much memory can be addressed by the paging solution?
b) How would I calculate how large must each page table be?

I'm not looking for the answer. I would just appreciate a clear breakdown.

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64 bit architecture allows 264 bytes to be addressed.

Six bytes is 48 bits, so the number of pages that can be addressed with a six byte page pointer is 248. Multiply that by a million to get the number of addressable bytes using 1 megabyte pages.

16 Gigabytes is approximately 230, and the paging solution already exceeds that capacity, even with a page size of 1 byte.

  • So if I understand correctly the breakdown would look like this: 2^48 * 2^10 which translates into 2^58 byte giving you and addressable amount of 2^18 TB? – Stevenson Oct 3 '16 at 2:08
  • Where did you get 2^10 from? – Robert Harvey Oct 3 '16 at 2:10
  • Page size is 1024 bytes (2^10), right? or am I mistaken – Stevenson Oct 3 '16 at 2:19
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    It says in your question that page size is one megabyte. – Robert Harvey Oct 3 '16 at 2:21

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