The 8086 addressing scheme is not a virtual one.
It is a physical addressing scheme that takes into account the limitation of the registers to the 16 bits of the processor architecture, while offering a larger address bus.
A better approach would perhaps have been to have 20 bit address registers, or a 32 bit address bus (and combine 2 registers for making one address register). It was technically feasible, because Motorola 68000 processor family had this nicer approach). But , this would have made the 8086 much more expensive.
The compiler had to take into account the addressing scheme through the concept of memory model. For example:
- the small memory mode assumed that all the data fits in 64K and all the code in another 64k, so that the code could load the segment registers once and keep them unchanged. Pointers were stored as a single 16 bit word.
- at the opposite the large model assumed that code and data could use the full address
Space, knowing then that segment registers had to be actively managed. Pointers were then stored with two 16 bit words (segment register+offset).
Between those extremes you had mixed models, in which either data or code was bound to a single segment of 64k.
From what I remember it was a painful scheme. Libraries had to be produced and shipped for each model. And lots of limitations: pointer arithmetic, array addressing, and memory allocation were bound to fit in 64k, even in large model.
So t summarise:
- the logical adresses are generated at run time (during the execution).
- the os loads the executable into memory, initialises the segment registers and hands over to the programme. From then, the programme has full responsibility.
- No, it is dividing something larger in smaller chunks so to cope with hardware limitations of the cpu
- Not relevant
Now if you want to understand this better, you'll have to look at the 8086 instruction set, and read about the memory models