This is an example of Memory-Mapped I/O:

enter image description here

So basically you access the device controller registers through memory.

Now my question is, when you for example write to the memory location that maps to the command register, will the value you write to this memory location gets copied to the command register in the device controller, or is the command register simply a pointer to this memory location (so basically there is only one copy of the value you will write, which only exists in memory)?


So basically you access the device controller registers through memory.

Not exactly, which is why the diagram in the question doesn't quite depict memory-mapped I/O.

Memory-mapped I/O uses the same mechanism as memory to communicate with the processor, but not the system's RAM. The idea behind memory mapping is that a device will be connected to the system's address bus and uses a circuit called an address decoder to watch for reads or writes to its assigned addresses responds accordingly.

The simplest example of this I can think of is the speaker in the Apple II, which makes a single click any time there's a read from or write to address 0xC030. The address decoder looks for the bits on the address bus to be exactly 1100000000110000, and when those conditions are met, a line on its output goes high, triggering the audio circuit that makes the click. More sophisticated devices might be stimulated to react to what's been put on the data bus (e.g., when the CPU writes to a control register mapped at one address) or place some of its own information there (when the CPU reads from a status register mapped to another).

As long as all of the timing rules of the bus are followed, the processor doesn't know or care that it wasn't RAM. (RAM, in fact, works exactly the same way.) All of this is done on a best-effort basis; the CPU can write to an address where there's nothing to respond to it and whatever was written gets lost in the ether; similarly, a read will result in random garbage. What's important to take from this is that there's exactly one read or write of the data, which is when it's on the bus. There's no writing to memory and then to the device, no pointers or anything else. The data exists on the data bus during that one read or write cycle and that's the end of it. The device may or may not store the value internally, but that's a function of the device, not the I/O mechanism.

As drawn, the diagram illustrates Direct Memory Access or DMA, where the device is instructed to negotiate for use of the bus to do an I/O of n bytes to or from address a in RAM and signal the processor when finished. This is almost always used for bulk data transfer (disk blocks, Ethernet frames, buffered graphics) and almost never for control and status, which is usually done memory-mapped.

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    So basically the CPU sees an IO device as just another RAM chip, and a device controller's registers are nothing more than regular memory locations (for example the control register is at the memory address 12345), and when the CPU wants to write a value to the control register, it simply writes to this address (for example: mov [12345], 5 will put the value 5 in the control register). Am I correct? – John May 31 '17 at 12:59
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    @John The CPU doesn't even know that RAM is RAM, but yes, you're correct. – Blrfl May 31 '17 at 13:20
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    @John, Fyi, and to add to the discussion, modern processor cache architectures mess with memory mapped IO, and so processors provide a way to turn off caching for some address ranges; that way each read and write instruction has the expected result of communicating with the device. – Erik Eidt May 31 '17 at 14:19
  • @Erik Eidt "modern processor cache architectures mess with memory mapped IO" What do you mean by "mess", you mean they cause problems for mapped IO? – John May 31 '17 at 15:20
  • @John What he means is that if the cache doesn't understand that an address is volatile because it's connected to a device, second and subsequent reads from that address might end up being done against the cache instead of the device. The same goes for writes. – Blrfl May 31 '17 at 15:34

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