Based on what I know so far, when you plug an IO device into an IO
port (for example, when you plug a printer into a parallel port), the
printer will be represented to the CPU as just another RAM chip.
It's better to think of this scenario as 2 separate devices, where one device (the parallel port controller) may or may not be presented to the CPU as just another RAM chip (and almost never is), and the other device (the printer) is not presented to the CPU at all. To send a byte to the printer, the printer's driver asks the parallel port controller's driver to send a byte, and the parallel port controller's driver tells the parallel port controller to send the byte.
Note that RAM chips have a special characteristic - reads and writes have no side effects. Because there are no side effects it's easy to use a few tricks to improve performance; like having caches, or combining smaller reads or writes into fewer larger reads/writes, or doing read or writes in a different order. A device's registers almost always do have side effects, and therefore they often can't be treated the same as RAM chips.
But can you send data to the printer by directly manipulating the pins
of the parallel port, that is, does the CPU have some instruction like
Let's start by assuming that the CPU has a physical address space, and that the physical address space is 4 GiB and that each physical address is a 32-bit address.
Let's assume that 2 GiB of the physical address space (addresses 0x00000000 to 0x7FFFFFFF) is used for RAM, and that for reads and writes in that area the CPU does tricks to improve performance (caching, etc).
Let's also assume that the remaining 2 GiB of the physical address space (addresses 0x80000000 to 0xFFFFFFFF) may be used for various devices (and the CPU does not do any tricks for reads and writes to this area).
Finally; let's assume that the CPU has instructions that read or write to any address. The same instruction that reads (e.g.) a variable in your application (with one address) can be used to read (e.g.) a parallel port controller's register (at a different address).
In this case there is no need for the CPU to have special instructions for devices.
For some CPUs there are multiple address spaces. For example, for 80x86 there is the physical address space (like what I've described above), but there is also an "IO port address space". In this case the CPU would have some special instructions that are used to access the special address space (e.g.
out instructions to access the "IO port address space") and these special instructions might have different behaviour to normal instructions that read or write to the physical address space (e.g. they might bypass the MMU, or involve completely different permission checks).