What architectures have "weak" memory models?

Question

I'm a long-time Java programmer familiar with the Java Memory Model. I'm starting to learn C#, and based on what I've learned so far, the C# memory model seems to be very similar to the JMM. This validates my previous understanding that the JMM reflects the characteristics of architectures supported by the JVM. The language requirements reflect the weakest guarantees of all the supported architectures.

But one difference I've noticed is in the way developers from Java and C# backgrounds talk about architectures. Where Java programmers speak of improperly synchronized code manifesting bugs on "some architectures", C# programmers tend to be more specific. For example, this article names Itanium as having a "weak" memory model:

The mainstream x86 and x64 processors implement a strong memory model where memory access is effectively volatile. ... The Itanium processor implements a weaker memory model.

I've only worked on x86 and x64, and I never knew what architectures imposed the mysterious requirements of the JMM that never seemed to matter when I tried to demonstrate the effects of violating them. Now I know of one.

What other architectures have "weak" memory models?

Answer 1

Nearly all RISCs have weak memory ordering models. ("Memory ordering" is a better term for this because "memory model" is too broad.) That means an ordering between memory accesses shall be explicitly requested with "barrier" AKA "fence" instructions. For x86 (any bitness), most barriers (but not all) are implicit.

Just in case, a Memory ordering topic is a good start. Another example of good description is C++ memory order constants.

Answer 2

A strong memory model is one where every load/store is a synchronizing operation; so it will order loads and stores around it.

A weak memory model is one that isn't strong; so there are plain operations loads/stores and synchronizing loads/stores.

The only order that needs to be preserved for plain/loads and stores is the data dependency order; something is typically done in hardware using the Tomasulo algorithm.

X86 is a strong memory model because it every normal load is an acquire load and every normal store is a release store. It does allow an older store to be reordered with a newer load to a different address due to store-buffers and hence doesn't provide sequential consistency but implements a total store order (TSO).

Some examples of ISA's with weak memory models are ARM and Itanium.

There are also hybrids like Sparc v9 that offer, TSP, PSO (partial store order) and RMO (relaxed memory order).

The JMM is also a weak memory model because it makes a distinction between regular loads/stores and synchronization actions (e.g. a volatile load/store).