Each data type must be aligned to a multiple of some number of bytes, for example a short int must be aligned to a multiple of 2 bytes, and an int must be aligned to a multiple of 4 bytes.

But why data alignment is used exactly, is it because the CPU can only read from memory in multiple of some number, so for example when the CPU is reading a short int, it can only read from the addresses 0, 2, 4, 6, etc.?

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    A more detailed answer will involve: (1) relevance in terms of older architectures; (2) relevance in terms of newer architectures; (3) impact on correctness; (crashing due to unaligned access) (4) impact on performance (due to software and hardware workarounds); (5) loss of atomicity; (6) architectures on which SIMD memory I/O alignments are different from non-SIMD instruction requirements. – rwong Aug 25 '17 at 4:36

Essentially, yes. It is possible for the CPU to read memory at non-aligned addresses, but it takes longer. This is probably a simplification, but it works something like this:

There are generally a set of data lines that go from the RAM controller to the CPU. If you have a 64-bit processor, for example, there will be 64 lines going from the RAM controller to the CPU. The RAM controller always pulls 64 bits (8 bytes) out of RAM and sends them along the data lines to the CPU. The CPU then has to mask out what it needs and throw away the rest.

There's a catch, though. The memory controller needs to be told by the CPU which address to read from. So there are address lines that go from the CPU to the memory controller. In order to simplify the memory controller, it always reads from an 8-byte-aligned boundary. The circuitry would need to be much more complicated to read starting at any address, as I understand it (though I'm no hardware engineer).

So if you want to read memory at a non-8-byte-aligned address, the CPU sends the address of the lowest byte it needs, the memory controller masks off the 3 low bits, reads 8 bytes and sends them back to the CPU. If you crossed an 8-byte boundary, then the memory controller also needs to read the next 8-byte range and send that back. The CPU then has to mask off the right number of bytes from each read, shift them and combine them back together into 1 8-byte number. (Or perhaps that all happens in the memory controller? Either way it takes longer.)

Even if you aren't reading 8 bytes, if you read from an odd address, it still needs to mask and shift the result to put it into a register.

Some older low-end CPUs did this even for some aligned reads. For example, I believe the 8088 only had 8 data lines, so a read of 16-bits always resulted in 2 reads and twice as many cycles for memory fetches. Once the data was on the CPU, it processed as fast as the 8086, though.

As mentioned in the comments there are even some CPUs that can't do any non-aligned reads presumably to simplify their design and lower their cost.

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    That is not true for all CPUs. Some CPUs (including many older CPUs) are incapable of fetching or storing from/to misaligned addresses. – Solomon Slow Aug 25 '17 at 2:52
  • You mean that they won't even do multiple reads and piece it together? If so, I'll add that to my answer. Thanks for the info! – user1118321 Aug 25 '17 at 2:59
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    The 8088 had 16-bit registers and 16-bit data paths on chip, but it only had an 8-bit path to memory. The 8086 was 16-bits internally and externally. Neither of those processors had any 32-bit registers. The first 32-bitter in that family was the 80386 which came in an "SX" variant (16-bits externally) and a "DX" variant (32-bits to memory). – Solomon Slow Aug 25 '17 at 3:01
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    Re, "Won't even ... piece it together?" For example, see How does the ARM Compiler support unaligned accesses? "On older processors, such as ARM9 family based processors, an unaligned load had to be synthesised in software. Typically by doing a series of small accesses, and combining the results." – Solomon Slow Aug 25 '17 at 3:04
  • And similarly the old sunws on SPARC approach of installing a bus error handler which fixed-up misaligned accesses on the fly. – Useless Aug 25 '17 at 15:36

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