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I know they can for addition and subtraction, but I'm not quite sure if they can for multiplication.

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As far as hardware goes, unsigned multiplication and signed multiplication are exactly the same (ignoring flags). When you multiply 11111111 and 11111111, the result is 00000001, regardless of whether the inputs are considered to mean -1 or 255.

That said, I don't know if the two operations would have a different effect on the carry and overflow flags, and how the difference is dealt with if so.

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    Re. flags, on x86, I believe both mul (unsigned multiply two n-bit integers, giving 2n-bit result) and imul (signed or unsigned multiply two n-bit integers, giving n-bit result) have the same effect on the carry and overflow flags: 0 if the upper word of the un-truncated result is 0, 1 otherwise.
    – Jon Purdy
    Sep 27, 2017 at 23:30
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    This is only true for non-widening multiply, like x86 imul reg, r/m and imul reg, r/m, imm. The widening forms that do 32x32 => 64-bit are different in the high half for signed vs. unsigned, and the FLAGS output also differs. This answer has unfortunately misled multiple people who linked it from SO questions or comments, e.g. this question and this comment. May 22, 2022 at 18:33
  • Same for ARM smull / umull, and RISC-V instructions to generate the high-half of a signed or unsigned multiply (and even mulhsu to do a signed * unsigned product). See also How many least-significant bits are the same for both an unsigned and a signed multiplication?. Of course there's only one instruction for non-widening multiply on most ISAs, because if you do it C style, like uint64_t prod = a * (uint64_t)b; widening the inputs before multiply, then yes this answer is true for 2's complement systems. May 22, 2022 at 18:33
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Can unsigned and signed (two's complement) multiplication be performed on the same hardware?

Assume an N bit width.

The trick is that the hardware can do a signed N+1 * N+1 wide multiplication, thus re-using most of the hardware when doing unsigned*unsigned, signed*signed or mixed signed multiplication.

2's complement N+1 operands can handle the entire range of intN_t and uintN_t. The final 2's complement 2*N + 1 product can simply save the desired bits into a 2*N destination.

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  • What is the source of this information? It is certainly correct that the problem could be solved this way. (This is exactly how it is done in FPGAs). But I'm trying to confirm if it actually is done this way in practical microprocessor implementations.
    – Harry
    Nov 27, 2023 at 15:29
  • My survey at the time indicated HW multiplication handled N+1. Six years later, the situation may differ. Nov 27, 2023 at 16:31

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