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The following quote is from this page:

While some CPU manufacturers implement a single address space in their chips, others decided that peripheral devices are different from memory and, therefore, deserve a separate address space. Some processors (most notably the x86 family) have separate read and write electrical lines for I/O ports and special CPU instructions to access ports.

I want to know what does "address space" means. This is what I think it means:

Say we have the following:

enter image description here

This is what happens when the OS starts running:

  • The OS will ask the memory controller for much memory the memory chip have, let's assume the memory chip have 2 GB of memory. Now the OS will pick a range of addresses that consists of 2 GB, let's assume the OS picked the range 30394 to 2147514042 (2147514042 - 30394 = 2 GB), now the OS will tell the memory controller to respond to requests on the memory addresses from 30394 to 2147514042.
  • The OS will do the same thing with the IO devices as it did with the memory (it will ask each IO device controller how much memory the IO device have...), now the important thing here is that the memory addresses that will be allocated for the IO devices will not be in the same range allocated for the memory (30394 to 2147514042), so for example if the monitor have 12 KB of memory, the OS will pick for example the range 104 to 12392 (12392 - 104 = 12 KB). Note that I assuming that the IO devices uses memory-mapped IO.

So basically "address space" means that both the memory and the IO devices will be in the same "pool" of addresses, and so the CPU can treat the memory and the IO devices as one logical memory chip.

Am I correct?

  • If you have one address space, the OS has one lookup table. This also implies if two addresses have the same value, they are most certainly pointing to the same place in memory. If you have multiple address spaces, you have multiple lookup tables, and therefore you have to add context to a lookup (OS has to know if address is memory or peripheral device for instance). The general tendency for 32 bit addresses is that a single lookup table pertains to 4GB of actual memory that it is mapped by. It can be less, but not more without having more address spaces or larger addresses. – Neil Oct 18 '17 at 8:59
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An Address Space is simply a range of allowable addresses.

An I/O address is a unique number assigned to a particular I/O device, used for addressing that device. I/O addresses can be memory-mapped, or they can be dedicated to a specific I/O bus. When referring to a memory-mapped I/O address, I/O uses the same processor instructions that you would use for addressing, reading and writing actual memory. When referring to a dedicated I/O bus, there are special I/O processor instructions that are used exclusively for read/write purposes on the I/O bus.

Naturally, when using memory-mapped I/O, one must dedicate a range of memory addresses set aside specifically for I/O, not memory. In the context of I/O, it is accurate to say that the range of memory addresses set aside for I/O is the address space where memory-mapped I/O takes place.

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The basic idea is pretty simple: a chip can have one bus to connect to memory, and a second bus to connect to I/O devices--or it can share a single bus between the two.

In practice, even a CPU that treats the two as separate doesn't usually separate them completely. For example, the original 8088 had a pinout like this:

enter image description here

With this, AD0 through AD7 carry the data and (depending on bus phase) the 8 least significant bits of the address. This goes for both I/O devices and memory. Then the IO/M pin (with a bar over the M) determines whether a particular read/write goes to memory or an I/O device (I/O device when it's high, memory when it's low).

If they'd chosen to, they could pretty easily have designated that pin as (for example) A20, so the chip would have one extra address pin, allowing it to address 2 megabytes of memory. Then somebody could write decoder logic that directed some subset of that range to I/O devices (and the rest to actual memory).

The big advantage of combining the two is fairly simple: as it stands it's basically split the address space in half: one half for memory, the other for I/O devices. That doesn't fit real usage very well though--in most cases, you'd probably be better off with (say) 64k for I/O devices, and the rest of the now 2 megabyte address space for memory.

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so the CPU can treat the memory and the IO devices as one logical memory chip... ?

Yes, in that the same cpu instructions to read/write RAM are used to read/write to the (memory mapped areas of the) devices — namely the processor's memory load and store instructions.

That being said, however, there are a few things to note, that even though the same processor instructions can be used, the software has to be considerate of device provided memory / communication areas in ways among the following:

Sometimes a device memory mapped communication area is designed to be to be written by the processor (to accomplish the O part of I/O), and other times to be read by the processor (to accomplish the I part of I/O). So, reading writeable device communication area may yield nothing but zeros or garbage rather than what was previously written by the processor (and writing readable may have no effect).

There is no reason for any RAM and/or any device memory to be contiguous, so there can be holes in the address space where neither RAM nor devices are mapped (rather than just one hole or absence e.g. at the end). Many devices expect a communication area to have a large alignment for the starting memory address, which is one source of holes between communication areas as address space is skipped over to reach proper alignment.

In order to accomplish I/O, we need to do more than read/write to the device address space: we have to follow a (device-specific) protocol telling the device what we're going to do, or listening to the device's ready signals, by using it's memory mapped (or I/O port accessed) control registers (which may their own communication area or part of another).

Devices are also (can also be) wired to the processor's interrupt lines, for asynchronous communication (in addition to being memory mapped), i.e. to signal the processor's attention.

The processors data caches can interfere greatly with memory mapped I/O. Because of this most processors have a mechanism to support uncached memory accesses. This is sometimes accomplished by using a (very high) bit in the address space to indicate whether accesses should be cachable or uncached. This is another reason for holes in the address space. (Some processors have all the same memory & devices accessible at two different physical addresses, where one of the mappings is cacheable, and the other uncached).

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