I’ve been reading about older processors (8080, 8086 and that) and i’ve seen that those older 8-bit processors had some 16-bit instructions through the use of register pairs. For example, on the 8080, the XCHG instruction exchanges the value from the HL pair and the DE pair. if these registers are 8 bits wide, and the internal bus is 8bits wide, how did the processor exchange the values with one instruction?


  • 2
    The 8086 is not an 8-bit CPU. It has a 16-bit external data bus and a 20 bit address bus. The 8088 is similar, but only has an 8-bit external data bus. Commented Jan 27, 2018 at 4:52

2 Answers 2


XCHG is a three micro-op instruction and takes more clock cycles than, say, a MOV. So right away we know it is doing something more complicated.

If you check this post, the exchange could be implemented either via a hidden register or via some clever bitwise math (three XORs = one exchange). Either way the bus size doesn't matter.

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    I think this answer is more relevant to today's processors and less clearly relevant to chips from the 1970s Commented Jan 26, 2018 at 23:34
  • Well, I worked with the 8088 and Z80 back in the day, and an XCHG type opcode always has costed more cycles than a MOV or LD, even double. So even though it takes only one opcode, the actual microcode being executed is more sophisticated. If there are more clocks being used then there is more bus bandwidth available while it is executing. The exception is something like XCHG A,A which is the same as a NOP.
    – John Wu
    Commented Jan 27, 2018 at 0:12
  • Is XCHG A, A exactly the same as NOP or does it attempt to “exchange” the values? does that whole instruction get caught by the decoder and execution just gets skipped for a cycle?
    – DylanG
    Commented Jan 27, 2018 at 0:56
  • There are two assembly instructions that map to the same machine instruction (90h). If you put a bunch of NOPs in your code then use a decompiler/disassembler, they will probably show up as XCHG AX, AX.
    – John Wu
    Commented Jan 27, 2018 at 1:07
  • The 90h opcode should display as NOP. I'd be surprised if any decompiler/disassembler displayed the 90h opcode as XCHG AX,AX. Commented Jan 27, 2018 at 4:54

It uses an internal temporary register. I pulled out my ancient copy of an original IBM 8086 Macro Assembler manual. The description of the XCHG instruction includes:

The contents of the destination (left-most operand) are temporarily stored in an internal word register.

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