Software Engineering Stack Exchange is a question and answer site for professionals, academics, and students working within the systems development life cycle. It only takes a minute to sign up.
Sign up to join this community
I’ve been reading about older processors (8080, 8086 and that) and i’ve seen that those older 8-bit processors had some 16-bit instructions through the use of register pairs. For example, on the 8080, the XCHG instruction exchanges the value from the HL pair and the DE pair. if these registers are 8 bits wide, and the internal bus is 8bits wide, how did the processor exchange the values with one instruction?
Thanks
XCHG is a three micro-op instruction and takes more clock cycles than, say, a MOV. So right away we know it is doing something more complicated.
If you check this post, the exchange could be implemented either via a hidden register or via some clever bitwise math (three XORs = one exchange). Either way the bus size doesn't matter.
MOV or LD, even double. So even though it takes only one opcode, the actual microcode being executed is more sophisticated. If there are more clocks being used then there is more bus bandwidth available while it is executing. The exception is something like XCHG A,A which is the same as a NOP.
NOP. I'd be surprised if any decompiler/disassembler displayed the 90h opcode as XCHG AX,AX.
Jan 27, 2018 at 4:54
It uses an internal temporary register. I pulled out my ancient copy of an original IBM 8086 Macro Assembler manual. The description of the XCHG instruction includes:
The contents of the destination (left-most operand) are temporarily stored in an internal word register.
