The instruction length can affect CPI, but usually only indirectly.
Generally speaking, a modern CPU will have paths from memory to cache and from cache to ALU that allow it to fetch an entire instruction at once, regardless of length1.
As such, it's fairly unusual for the instruction size to directly. At the same time, a CPU never has unlimited cache space. A larger instruction occupies more cache space, limiting the number of instructions that can fit in the cache. That, in turn, leads to a higher likelihood of cache misses, in which case the CPU can end up waiting for main memory.
As to whether CPI is always variable: yes, at least almost always. In particular, resource dependencies between instructions can limit the amount that can be done in any given cycle. Consider a completely serialized task, where each step of the task depends on the previous step.
In such a case, it's essentially impossible to execute more than one instruction per clock (short of re-structuring the problem, which is generally beyond what any CPU will attempt).
At the same time, a modern, high-performance CPU will almost always have at least some capability to execute more than one instruction per cycle if there aren't any dependencies between them. As such, something like:
OR r0, r1, r2
OR r3, r4, r5
...can normally be executed in parallel, if the processor has resources available to do so. We need to know more about the preceding instructions before we can say how long it'll take to execute those instructions. With more complex instructions that involve access to data that might (or might not) be in a cache, etc., the picture becomes even more complex.
- Though this is not always guaranteed. For example, an x86 supports instructions with up to 16 bytes of prefixes (plus the instruction itself), so although it's rare in practice, a single instruction can be too large to transfer in a single cycle, at least on some hardware. Even in this case, a large instruction doesn't necessarily reduce CPI--with a trace cache, what gets stored isn't the raw instruction.