Could someone give a hint, in plain english, what it means to debug an HDL program?
Debugging is understandable as far as it concerns software but at this low level what does debugging means?
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Debugging HDL normally has 2 major steps after just looking at the code.
Analysing the logic: this is normally done but simulating the behaviour of the hardware and the usual software process kicks in, but its abit more convoluted.
Analysing the behaviour on an real system, which sometimes differs due to timing etc: this is not easy and usually involves blinking LEDs and swearing.
For debugging, use a HDL simulator. Modern HDL simulators have full-featured GUIs, complete with a suite of debug tools. See wikipedia list of HDL simulators for some examples.
HDL debugging used to mean to me, that the Design or Test Engineer would write a TestBench code to create vector inputs (matrix of logical inputs) to test all output vectors against the design spec* to try all variations of inputs and check the expected output vs the model and "the spec*" after the design was completed.
The discrepancies in the validation of the timing or functional logic were part of the debug process. Often this process was part of a larger process called Design Verification Testing or DVT for product testing that included environmental limits and supply/component tolerances.
Normally Design includes DFT and DFM so fault detection, reporting and correction are included with metrics on fault coverage for in-circuit and/or self-test.
In so far as automated GUI simulation can be done, one still has to define the "hierarchical input process output" specs* or HIPO as IBM used to call it for any design. This would start as a high level description. That is part of the Design Spec.