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In a SyML/UML activity diagram, how do you implement an OR gate ?

There immediately came to mind to use a merge node. But does a merge node always have to come after a decision node?

Also, I have seen an action with two inputs where each input has a multiplicity definition, e.g., [0..1], but how could this be used to implement an Or gate where the action would be fired if at least one of the inputs contained a token?

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    SysML has it's own definition (which I don't know well) compared to UML. In UML there are clear rules where and how to "or" flows. – qwerty_so Feb 14 at 11:40
  • >> Does this help: uml-diagrams.org/activity-diagrams-controls.html#merge-node ? – Christophe 6 hours ago It says there: "Merge node is a control node that brings together multiple incoming alternate flows to accept single outgoing flow." So it looks like my first thoughts were good thoughts. Thanks, Christophe. I will wait a bit for a few more answers. – user2930201 Feb 14 at 13:29
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    You implement an OR gate by using the symbol for an OR gate. It looks like this. Since we all know there is no such symbol in UML, I assume you meant to say something else besides "OR gate." – Robert Harvey Feb 14 at 17:38
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    This could also help: UML Activities. – Theraot Feb 14 at 19:51
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The question is tricky, because an or-gate processes two concurrent input signals to produce one output signal. But in the activity diagram you manage control or object flows: the semantic is different. So the answer depends a little bit of what you try to represent:

Option 1: the sequential or

If you mean to say that some flow A or some flow B could happen and then something is done, (i.e. A and B are alternative flows), then you may use a merge node.

You may merge any flows, whether or not they are resulting from a same decision node or not. The only constraint is that the merge does not require synchronisation of concurrent flows.

Option 2: the concurrent or

If you mean to say that two concurrent flows A and B shall happen, but that if one happens then if it sufficient for the flow to continue, then you should use a join node with an {or} joinSpec. A joinSpec allows to express a logical condition between the incoming tokens or objects on each input flow. You may even use the name of the incoming flow (e.g. {joinSpec=a and (b or c)}.

Note: No difference here between SysML and UML: SysML has both UML merge nodes and join nodes with the same meaning.

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    I wasn't aware of that joinSpec (there are examples on p. 391 of UML 2.5). – qwerty_so Feb 14 at 21:26
  • Thanks, again, Christophe, for the comprehensive information. See below for my "comment concluding the thread". – user2930201 Feb 23 at 13:11
  • @user2930201 Thanks for this feedback. I confirm that my answer was indeed for software and not for a hardware gate. Two inputs may come from two independent threads (in which the join node would probably be the right option), or they may be sequential in a complex flow (where the merge node would be the right approach). The key difference for laking the choice is: is there a need to synchronise parallel independent flows or not. Keep us posted when the new question is ready :-) – Christophe Feb 23 at 16:47
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To add to the discussion above, you need to be clear whether you need a "merge" node or a "join" node.

Every path through the activity diagram follows a token flow.

if A and B are inputs and C is an output:

  • Merge Node: every time an input appears on A or on B an output token will be generated on C. That is, neither input waits for the others.
  • Join Node: when a token arrives on A, it waits until a token also arrives on B and then generates an output token in C.

If you are trying to model boolean logic...(you would probably be better off in SysML than UML...but that is not important here) the join node will probably be more realistic because the gate will make its decision on a clock edge. However, this is still not perfect because absence of an input will be taken as an input...not really a correct representation of the logic circuit.

Chewing further on "OR NODE" as representing a logic circuit....if this is what you are doing, I would recommend two things:

1) Use SysML rather than UML - SysML is built on top of UML and is less software-centric 2) Move up a layer of abstraction and think about functional and information flows. What information is moving from where to where?

Trying to model the wires and the transistors in either UML or SysML is counterproductive. The strength of model-based engineering techniques is NOT in replacing the low-level specialty design tools. The strength of the modeling tools is in getting a diagram on the screen in a conference room in which 2 hardware engineers, 1 software engineer, a customer support engineer, an accountant, and a lawyer can all have a sensible discussion about what the system is supposed to do.

Hope this helps!

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  • I should have stated that this is a software OR gate in a software process. But anyway, it is still a logical OR gate, whether it is a SW or HW, so what the heck... – user2930201 Feb 15 at 23:39
  • In an even greater question I have about the OR gate (than how do you do it) is: given that simple logical gates are such basic elements in system—whether HW, SW, or logical— why did I not succeed in finding textbook material about this on the internet. And why is the answer so complex? It's only an OR gate... – user2930201 Feb 16 at 0:00
  • @user2930201 It's not "just". You are not telling us what your intension are. A hammer can be used manifold. Not all uses are meaningful. – qwerty_so Feb 16 at 16:02
  • How do I upload to this forum a pic of what I am doing? – user2930201 Feb 18 at 9:22
  • Ok - Can you all see this: drive.google.com/open?id=1Llzx_Hjidt0pa7y7Q3IDJPpov1STLn0k – user2930201 Feb 18 at 9:25

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