For example I have a static C++ array {'d', 'o', 'c', 's'}. And I have x86 architecture, with 32-bits length words.

I want to replace letter c with g. As far as I understand, when we make a read operation from a byte addressable RAM, CPU always reads 1 word from it. So it will read the whole array.

After CPU will read the array, I will replace letter c with g and write it back to memory.

Will CPU write 1 bytes or 4 byte in RAM?

If it writes 4 bytes, what's the point of using byte addressable memory instead of word addressable?


Let's consider another example. The CPU uses 32 bits words. We have an array of 4 bytes in RAM. It starts at address 0x000:

0x000: 1110 1111 0000 1100 [1110 1111] 0000 1100 // we want to update byte in brackets
0x003: ....
0x007: ....

Since RAM is byte addressable, each cell contains exactly 1 byte. So, theoretically, we can read or write 1 byte using single memory access. But since computer has 32 bits bus, CPU always reads 32 bits using single memory access.

So as far as I understand CPU reads the whole word into its register:

1110 1111 0000 1100 [1110 1111] 0000 1100

Then it updates 3rd byte in this register (for example with 1000 1111):

1110 1111 0000 1100 [1000 1111] 0000 1100

And I don't understand what’s next. [Main question] Does CPU write all 32 bits from register to RAM or only 8 bits?

[Answered] If it updates 32 bits, what’s the point of not using word addressable RAM which works exactly the same? According to answers below we still did it because of our past and Sneakernet.

  • Am I right in thinking that your essential question is "why does a CPU have instructions which can address and manipulate memory at a resolution smaller than its native word size"? The simple answer is convenience - many CPUs are backwards compatible (that is, "binary compatible" which means they continue to support instructions which are narrower than their native word size so that old compiled software continues to run seamlessly), and computer programmers are also accustomed to the notion of the 8-bit byte and pointers to byte addresses, as being the basic elements of computing.
    – Steve
    Mar 15, 2020 at 0:37
  • Yeah, it is definitely possible to change only one byte of RAM
    – user348453
    Mar 15, 2020 at 23:41
  • Note that it is common for 32-bit cpu to use 64-bit bus. Processor's "word" has nothing to do with memory.
    – user289860
    Mar 16, 2020 at 18:51
  • 3
    CPU always reads and writes 64 bytes from memory. These are called "cache lines".
    – user253751
    Mar 17, 2020 at 10:44
  • This... reeks of a homework question. I'm VTC.
    – T. Sar
    Mar 17, 2020 at 11:56

7 Answers 7


The internet.

When you have multiple computers networked together there is no such thing as "the word size". Every computer has its own idea how big it's bus is. But they all agree on bytes (even if they can't agree on byte order). So we keep making bytes addressable. It helps with compatibility issues. It's a carry over from the days of 8 bit computing when that was the bus size.

The sneaker net.

Even computers that aren't physically connected still share data using removable media. They need some kind of agreement on how big addressable units of memory are. Here we also settled on 8 bit bytes. It's why ASCII and EBCDIC fit in bytes.

These traditional forces are why when bus sizes grow they typically grow into something divisible by 8. It's hard to escape your past.

Is it possible to update exactly 1 byte in RAM?


It has to be. It's just a question of how that's done. Exactly how it's done is architecture dependant.

Typically the bus itself is "byte addressable". So just because I've sent you more bytes than you need doesn't mean you have to use them all.

I've found a good explanation of that here.

  • 1
    @NoNameQA better? Mar 14, 2020 at 13:06
  • 1
    Well of course there are performance issues. Unused bytes don’t transfer data. But they don’t stop this from working. How many go unused is in control of those who define the data structure. Mar 14, 2020 at 14:06
  • 1
    I'm not really following this reasoning. There is no necessary connection between byte addressability and the native word size. And as for networking or removable media, these share no relation at all - a floppy disk for example was typically sector addressable (512 bytes), with sector-at-a-time updates.
    – Steve
    Mar 15, 2020 at 0:06
  • 2
    I'm not following why that is the case. Main memory addresses are rarely if ever used outside an individual machine, so I don't see why communication with another machine would be impugned if one particular machine addressed main memory in 16-bit, rather than 8-bit chunks. Also at the physical level, many removable storage mediums are not byte addressable, or byte updateable, and many wired communication protocols are serial (that is, one-bit-at-a-time).
    – Steve
    Mar 15, 2020 at 11:01
  • 2
    16 bit is divisible by 8. Try to work with ascii on a 6, 12, or 18 bit computer. You either end up zero padding at the bit level or you end up on the sad side of a greatest common denominator problem. Let everyone use whatever bus size, without regard to 8 bit bytes, and the GCD problem ends up having a combinational explosion. Not every data structure is naturally byte aligned. Even ascii has an unused bit. But because of 8 bit bytes being the convention that’s the end of the addressability issue being the cause of any more padding. Mar 15, 2020 at 13:56

The C Standard requires that the implementation must be able to read and write single bytes. If you have an array char a[100] and one thread increases a[0] by 1, while another thread increases a[1] by 1, it is required that the implementation doesn't introduce any race condition.

This is the case even if your code runs on a server with two sockets (that is two independent CPUs) and these two threads are on two different CPUs.

There will be a lot of bus traffic going forth and back, and it won't be very efficient, but logically each thread can read and write a single byte.


Logically you will update just the byte. Note that a byte is already a logical concept. On a hardware level there are no bytes. In a modern computer there will be a lot of electronics in between the registers of the CPU and the memory cells of the main working memory, the CPU (or should I say instructions) have no direct control over the memory anyway. There is a lot of optimization and caching going on because transistors are cheap these days.

It depends on the memory technology whether ultimately 8 switches will flip or an entire row of multiple kilobytes will be rewritten. For us software people it is nothing to worry about, we just want to know how quick we can write that logical byte. And maybe how that will play out if we write a lot of bytes, random or sequentially.

So the answer is you cannot know what exactly goes on at the hardware level and for your own sanity you should not care too much.

  • Thank you, I totally understand it. My point is if I want to update single byte, is it possible in byte addresable RAM? Or CPU will update the whole word which contains my byte? If CPU can update single byte, than it make a lot of sence why we use byte addressable RAM. But if not, what the reason behind it? I mean in word addressable RAM CPU reads and updates the whole word. So if CPU can not work with single byte, therefore it do exactly the same thing as byte addressable RAM.
    – No Name QA
    Mar 14, 2020 at 11:55
  • @No Name QA We use byte addressable memory partly because of legacy reasons. A byte is the smallest useful power of 2 in western culture so when bits still were expensive that is what was modeled and turned into physical memory. The CPU does not read every byte/word before it is written by the way. Mar 14, 2020 at 12:01
  • Please take a look at my original question, I have updated it.
    – No Name QA
    Mar 14, 2020 at 12:45
  • Although they are hard to find now days, surely you are not aware of 4-bit CPUs? And if you want to go even more extreme there is bit-slicing.
    – Peter M
    Mar 14, 2020 at 22:57
  • @Peter M I am aware of this legendary thing which is widely recognized as the first microprocessor but it was a short-lived step-up to 8 bits and we are still using 8 bits today. So it did not seem relevant to the question. spectrum.ieee.org/tech-history/silicon-revolution/… Fun fact: if you look at the picture you can tell in the old days they used to make microprocessors out of wood. Mar 15, 2020 at 6:55

Note: This is not a full answer. This is intended to introduce a mental framework to help anyone parse the existing varied answers to this questions.

(0.A) Before you start reading: Are you on an educational program, studying for a course, or preparing for an examination? If this is the case, the institution that is in charge of your study is also in charge of deciding what answers would be accepted. Therefore, your best bet is to stick to what they have decided, rather than looking for answers elsewhere. This is true even if their answers are wrong. You simply parrot the wrong answer that they would accept, while reminding yourself not to stick to this answer once you finish your study.

(0.B) The type of computer systems also matter. For most people (students and software programmers), the two types that matters are: "general purpose computers" and "embedded systems".

If you need answers for "embedded systems", users of the Electronics Stack Exchange will offer more relevant answers. Be warned that today's "embedded systems" are moving towards biscuit-sized PCs, which means a lot of practitioners nowadays are using miniature general-purpose computers to do the work of what embedded systems used to do. In embedded systems of the last decade, hobbyist circuit boards may contain discrete electronic components, such as "32k x 8-bit SRAM", etc. These are the truly "byte-addressable" memory running on 4-bit or 8-bit bus. The current trend of using miniature general purpose computers imply that those discrete electronic components may become a thing of the past.

If you need answers for, say, "mainframe computers", or computer architectures that have since been discontinued, please refer to Retrocomputing Stack Exchange.

If you need answers for "8-bit computing", both sites (Electronics; Retrocomputing) will offer useful advice.

(1) The answer as seen from a C programmer: see gnasher729's answer. Note that, the C standard's definition for a byte is that it can hold "at least 256 different values", implying at least 8 bits (or equivalents), without requiring that it is exactly 8 bit.

(2) The answer as seen from a programmer who writes assembly language or machine code (the binary code that the CPU would execute): They will see what the Instruction Set Architecture (ISA) has specified for. The x86 ISA allows for instructions that updates one byte at a time. However, there is no guarantee that updating a single byte (8 bits) would take one-eighth the time for updating a 64-bit value. (It is very well possible that updating an 8-bit value in memory could take the same amount of time as updating a 64-bit value in memory.)

(3) The answer as seen on the CPU cache: see user253751's answer, first paragraph. It may require understanding of cache coherence protocols. Refer to the Wikipedia article for more information. On Intel architectural documents, the performance of CPU memory bus is measured in "transactions" ("MT/s": mega-transactions per seconds, "GT/s" giga-transactions per seconds). A "transaction" refers to the minimum unit of data transfer per command.

(4) The answer as seen on the memory bus: SDRAM bus commands are issued by the memory controller to the RAM modules. You will need to read the section burst ordering and burst length in order to understand a technically accurate answer. On SDRAM (and later standards, such as DDR4), "word size" is 64-bit. See Wikipedia article on this topic: Synchronous_dynamic_random-access_memory@Commands

(5) The answer as seen on the electrical control circuits that reside on the SDRAM module: see Martin Maat's answer, second paragraph.

(6) The answer as seen on rows of transistor-based memory cells on the memory chip: see user253751's answer, second paragraph. An entire row of memory cells are updated at once. ("Row" is the commonly used terminology when referring to SRAM and DRAM. "Block" is the commonly used terminology when referring to non-volatile random-access-memory, NVRAM. They both refer to the smallest organization of memory units that must be updated all at once.)

(7) The answer as seen from the Operating System (OS). As long as an application is accessing its own memory, and it is not the first time the application touches the memory page, the OS will not contravene. Normally, the answers (1 - 6) will apply as usual. However, several situations will require OS intervention: (1) the application has asked the OS to give it a fresh new empty page, the OS has granted it (and gave it the memory page address to that new page), but has yet to prepare it. In this case, the first time memory access will trigger some page preparation operations. This may involve writing more than one byte of data to the memory. (2) the application has tried to access some memory address it is not allowed to. In this case, the OS will stop it.

  • Darn ... it seems that I can only up-vote an answer once. Mar 17, 2020 at 21:51
  • @MikeRobinson Reminder: this is not an "answer" in itself. My entry wouldn't have existed if others had not contributed their parts at various abstraction levels to this question. (I should have marked it "community wiki", though. I don't intend to "own" this.)
    – rwong
    Mar 17, 2020 at 22:01

The CPU (at least, my CPU) always reads or writes 64 bytes at a time. This is called a "cache line". If you give it an instruction to write one byte, it will read 64 bytes, update 1, and eventually, it will write 64 bytes. (If you keep updating the same 64 bytes, it won't need to keep reading and writing them over and over. Also, the CPU can store many groups of 64 bytes)

Memory chips (at least, some chips) always read or write 8192 bytes at a time. This is called a "row". If the CPU tells the memory chip to write 64 bytes, the memory chip will read 8192 bytes, update 64 bytes, and then write 8192 bytes. (If you keep updating the same 8192 bytes, it won't need to keep reading and writing them over and over. The memory chip can only store one group of 8192 bytes, but there usually isn't a speed problem caused by reading and writing them)

Byte addresses allow you to tell the CPU to write 1 byte. You can't tell the CPU to write 1 bit, because memory isn't bit-addressable. You have to use bit-shift and mask instructions to tell the CPU to write 1 bit. If the memory was cache-line-addressable instead of byte-addressable, you could only tell it to write 64 bytes. You'd need to use bit-shift and mask instructions to write 1 byte.

  • And hardware is very good at those sorts of shifts and masks. So if byte acces is a common operation, why not keep it in the memory access hardware rather than taking up cpu executor cycles. Mar 17, 2020 at 10:57

All modern microprocessors physically read and write to memory in units larger than one byte, but allow the content of individual bytes to be changed.


This question is so architecturally specific that if you have any cache on the processor, then technically no. However, even with caching, you might not even change 1 byte depending on the context.

I’m curious why you are not considering why we are using dynamic ram, dynamic ram is in a constant state of being refreshed. That is it is constantly being rewritten in order to maintain the content.

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