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A Makefile is a representation of a depency graph. The files are the vertices, for example somefunctions.h, somefunctions.c and myprogram.c are the "input" vertices (is there a formal word for this?) and somefunctions.o and myprogram are the "output" vertices (again, correct word?).

Then the edges of that graph are somehow related to invocation of the compiler and linker in this example. But not one-to-one, since myprogram would have three edges connected to it (somefunctions.o, somefunctions.h and myprogram.c), but only one call to the compiler to create myprogram. What would be the correct way to describe that relation?

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Your build-dependency graph just maps the path of change propagation and not the build process:

enter image description here

To map the build process, you’d need to add intermediary build-nodes that are target of the dependency-edges, and add build-edge from the intermediary build-node to the corresponding target-node. The build-edges correspond exactly to the build commands of your makefile:

enter image description here

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  • I notice that there's one build command node for every output node. – user253751 Jan 15 at 20:15
  • @user253751 I don't have the makefile of question, but the idea here is that every orange node corresponds to a makefile target, that creates an output. Of course, if no myprogram.o is used there, you'd remove the corresponding intermediary orange and green nodes which would not appear in the makefile – Christophe Jan 15 at 20:19
  • Hm, I guess that makes sense. But now I have two different types of vertices, and the graph also becomes larger. I was hoping to avoid that, but maybe that's not possible. – Psirus Jan 18 at 7:28
  • @Psirus visually, you could reduce the build-nodes to a point, and remove the arrow head for dependencies: the diagram would appear more compact, and the dependencies and build-edges combined would look as Y shaped arrows. – Christophe Jan 18 at 9:26

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