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https://en.wikipedia.org/wiki/Memory_coherence says:

Memory coherence is an issue that affects the design of computer systems in which two or more processors or cores share a common area of memory.[1][2][3][4]

In a uniprocessor system (whereby, in today's terms, there exists only one core), there is only one processing element doing all the work and therefore only one processing element that can read or write from/to a given memory location. As a result, when a value is changed, all subsequent read operations of the corresponding memory location will see the updated value, even if it is cached.

Conversely, in multiprocessor (or multicore) systems, there are two or more processing elements working at the same time, and so it is possible that they simultaneously access the same memory location. Provided none of them changes the data in this location, they can share it indefinitely and cache it as they please. But as soon as one updates the location, the others might work on an out-of-date copy that, e.g., resides in their local cache. Consequently, some scheme is required to notify all the processing elements of changes to shared values; such a scheme is known as a memory coherence protocol, and if such a protocol is employed the system is said to have a coherent memory.

https://en.wikipedia.org/wiki/Cache_coherence says

In computer architecture, cache coherence is the uniformity of shared resource data that ends up stored in multiple local caches. When clients in a system maintain caches of a common memory resource, problems may arise with incoherent data, which is particularly the case with CPUs in a multiprocessing system.

In the illustration on the right, consider both the clients have a cached copy of a particular memory block from a previous read. Suppose the client on the bottom updates/changes that memory block, the client on the top could be left with an invalid cache of memory without any notification of the change. Cache coherence is intended to manage such conflicts by maintaining a coherent view of the data values in multiple caches.

What are the differences between memory coherence and cache coherence? They look identical.

Thanks.

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  • Since "cache" - in this context - is a specific type of memory, I guess cache coherence is just a specific case of memory coherence, or part of a coherence model. I did not read it, but it seems this ebook might be useful for your: A primer on memory consistency and cache coherence
    – Doc Brown
    Commented Feb 6, 2021 at 14:17
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    It would help answerers tremendously if you could explain what, precisely unclear to you about the texts you quoted, which parts you understand, which parts you don't understand, what research you have undertaken to try and understand those parts, and why that research failed to yield satisfactory results. This benefits both yourself and the answerers, because the answerers avoid wasting time explaining this you already know or repeating things you already tried and failed to understand. It also helps you avoid getting useless answers repeating things you already know, or repeating things
    – Jörg W Mittag
    Commented Feb 6, 2021 at 14:59
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    … you already studied and didn't help you in your journey to understanding. In particular, since those are two separate sources, it would help tremendously, and save everybody a lot of wasted time, confusion, and effort, if you could verify that the terms used in those two sources are defined in a way that is consistent with each other. Because if the definitions are not consistent, then there is no point to even start comparing them; your question will essentially become non-sensical at that point,
    – Jörg W Mittag
    Commented Feb 6, 2021 at 15:01

2 Answers 2

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When you use caches, data isn't usually written to memory immediately. Consider two cores A and B with caches X and Y and memory M.

If A writes data, it will update cache X but not immediately memory M. If B tries to read this data, the old version might be in cache Y (and B gets the wrong data), or Y might transfer the data from M to Y (and B gets again the wrong data).

The most efficient way to solve the problem would be to move the data from X to Y, avoiding writing to and reading from memory altogether. That would be "cache consistency".

And since this is all quite inefficient, processors won't do this automatically. And most programming languages say that if you read data modified by another thread, that's your own problem until you use special precautions.

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  • This information is not correct. Caches are always coherent on modern processors; the only type of processor I know with incoherent caches is a GPU. Apart from that, modern caches are write behind caches, not write through (wt is very inefficient). So in theory, there is no reason for a modified cache line to end up in main memory. There are some limitations on some cache coherence algorithms like MESI whereby a read by a different CPU of a dirty cache line force the cache-line to be flushed to main memory. But MOESI (AMD) resolves that problem. Also when there is a shortage of cache.
    – pveentjer
    Commented Jul 11, 2021 at 15:30
  • Processors do this completely automatic and it is pretty efficient as long as you don't have contention. As long as there is no contention, the CPU can use the cacheline without any form of cache coherence traffic or communication with main memory.
    – pveentjer
    Commented Jul 11, 2021 at 15:32
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Cache coherence defines some ordering of loads/stores over a single address.

Memory consistency defines some ordering loads/stores over multiple addresses.

When looking at the wiki, it seems that memory coherence is the same as cache coherence.

For more information see (you can download the book for free) https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049

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