I have been implementing a finite state machine which basically ensures configuration of the external chip which communicates with my MCU via I2C. The skeleton of the configuration state machine looks like this:
Whereas the Configure Register N states are state machines in their own. It is pretty simple state diagram but there is one complication. The chip can asynchronously generate a "fault" event which is signalized via assertion of the "fault" pin. State of the fault pin is read with the same period with which the state machine is executed. Service of the fault pin activation is based on another state machine. So the basic state diagram incorporating the fault pin activation service looks like this:
At first glance there are several repeating patterns in the state diagram. At first the state diagram for the register configuration and secondly the state diagram for fault pin activation handling. I would like to exploit these patterns and avoid of repeating the same code at several places. Can anybody suggest me any solution?