How are physical memory addresses actually determined or 'created'. What is the process where the byte blocks have a memory address assigned to it?

I understand that this is determined during boot up, before the BIOS is executed. But not exactly sure how or what the process is.

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    Worth a read: Wikipedia's Virtual memory.
    – mouviciel
    Apr 23, 2021 at 10:08
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    @mouviciel: worth noting this question is not about virtual memory addressing, only about physical memory adressing
    – Doc Brown
    Apr 23, 2021 at 14:37
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    @DocBrown: Therefore, it does not belong to Software engineering... more to Electrical Engineering.
    – mouviciel
    Apr 23, 2021 at 14:41
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    I would strongly suggest you check out Ben Eater's Build a 65c02-based computer from scratch series. It goes step by step, building a computer with memory, a display, and a keyboard input. You'll learn about address spaces, assembly, interrupts, clocks and more.
    – Alexander
    Apr 23, 2021 at 15:59
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    There are two very good answers here already so I'm just leaving this as a comment to emphasize them. ALL RAM CHIPS EVER MANUFACTURED HAS ADDRESS THAT STARTS AT 0! It is the responsibility of the motherboard designer to map EACH SLOT of RAM to a memory range. It used to be done using a chip called a memory controller which translates the CPU memory address to physical RAM slot. Nowdays modern CPUs have memory controller built in so it is the responsibility of the CPU designer to give enough features (tools) to motherboard designers for this
    – slebetman
    Apr 23, 2021 at 18:34

5 Answers 5


I think the other answer has confused you slightly, and again for low level questions like this I suggest you learn one of the 80s microcomputer or modern microcontroller architectures.

saying that the memory addresses are assigned during manufacture of the RAM chips

This is basically wrong. The chips themselves do not know about absolute addresses from the programmer's point of view.

The key you need to understand is a "multiplexer". Imagine that you have an 8-bit computer with 8-bit addresses, wired to a single RAM chip. Inside the chip, a multiplexer decodes the 8-bit address to one of 256 values, effectively turning on one of 256 wires. That connects a particular group of eight cells in the chip to the data bus, enabling the processor to read or write them.

So far so good. Now you decide the architecture needs more RAM. So you expand the address bus to 12 bits. But each RAM chip only accepts 8 address bits. So you need another multiplexer: this time you take the top 4 bits and decode them to one of 16 possible values, and use that signal to decide which of the 16 RAM chips in the computer to communicate.

Which address maps to which hardware is determined by the address decode logic, the multiplexer in the middle.

It is usual for CPUs to start executing from a fixed memory address, often near the "top" of the address space. Maybe our 12-address-bit CPU starts from 0xF00, for example. In that case it's useful to arrange the hardware around the CPU so that 0xF00 is mapped to a ROM. This is the concept of a "memory map".

how would the computer know the addresses, does it make a massive request during boot up, or what's going on?

There's usually a mix of techniques. The processor will blindly start at some address, so it's the responsibility of the motherboard to provide some code at that address, such as a PC BIOS. That code will then probably go off and scan the memory - DIMMs have a small ROM chip on a separate serial bus that describes how big they are and what speed they support.

On the other hand, smaller systems may have an entirely fixed memory layout chosen by the designer.

PCI cards may also be mapped into the memory space by the BIOS at boot time. This enables the processor to find the video RAM (often on a separate card) and start up the display.

  • Thank you for the answer. I have to confess, I'm not good with the electronics side. I do understand when you say the chips don't have an absolute address. I believe the memory controller has a part to play in creating the addresses, but I'm not entirely sure how. Also, you spoke about a sort of scan occurring when the BIOS is loaded, but my understanding is that the memory has already been addressed before the BIOS loads, I could be very wrong though.
    – jdow
    Apr 23, 2021 at 19:39
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    The BIOS is in the memory map - but as a ROM (read only memory). So yes, executing the BIOS is done through the CPU's memory interface. The controller doesn't create the addresses, it maps them - ie it defines what happens when a particular address is accessed.
    – pjc50
    Apr 23, 2021 at 19:57
  • Thank you for clearing that up. It helps to make a lot more sense of things. So if the CPU was requiring data, it would send a read request to the memory controller, right? If so is that what mapping is, or is it something else similar to memory mapped I/O?
    – jdow
    Apr 23, 2021 at 20:07
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    Actually DRAM chips do have rows, columns and banks (hence the need for the RAS, CAS and bank-select signals). The memory controller logic deals with this, it is abstracted from the CPU.
    – Rodney
    Apr 24, 2021 at 8:02
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    @jdow Yes, as Rodney says there are rows/columns inside DRAM chips. Memory mapped IO is indeed using the word "mapped" in the same sense; the CPU makes a read/write request on the memory bus, but it gets routed to something that isn't memory, or is inside a peripheral.
    – pjc50
    Apr 24, 2021 at 10:59

Reading from the other answers, I think one of misunderstandings you're operating under is that memory addresses are somehow globally unique, like IP addresses, MAC addresses, or phone numbers. That's not the case.

Fundamentally, a RAM chip just has the following things:

  • Some number of address lines, called the address bus
    • (this determines the maximal number of addressable words within the chip)
  • Some number of data lines, called the "data bus"
    • (this determines the size of a word, the size of data that can be read from a single address)
  • A "write enable" (WE) pin
    • When enabled, pulsing the clock will cause the value of the addressed memory cell to be set to the value read from the data bus
    • When disabled, pulsing the clock will cause the value of the data bus to be set to the value read out from the addressed memory cell
  • A clock pin. When pulsed, the value of the address bus is read/written, depending on the WE pin
  • A "chip enable" (CE) pin, which either makes the chip enabled, or not.
    • When enabled, the chip operates as described

    • When disabled, the data bus is set to a 'high impedance' state.

      This is critical. It allows multiple chips to share the same data bus. Consider what would happen in this example: bit 0 of chip 0's databus might be low, while bit 0 of chip 1 is high (e.g. 5V). Since chip 0 and chip 1 share a databus, their two data bit 0 pins are connected together. If they have different values, such as the case here, you have 5V connected to 0V. This is a short circuit, and the magic smoke will appear.

      Using the chip enable pins, you can have it so that disabled chips effectively "disconnect" themselves from the rest of the circuit. So long as only one of the chips is active at a time, then there is only one chip connected to the databus, and thus no shorts will happen.

You can imagine a 256 byte RAM chip. Addressing 256 values means that the address space of this chip ranges from 0b0000_0000 (0) to 0b1111_1111 (255). But what if you want to have a computer with 512 bytes of RAM, but there are no 512 byte chips in production?

Well, you can use two 256 RAM chips, together! Each one has 256 byte-sized memory cells, with their own 8 bit buses that accept values from 0 to 255. Now, notice that addressing 512 bytes would need a memory space ranging from 0b0_0000_0000 (0) to 0b1_1111_1111 (511). This needs a 9 bit address bus. But each of our chips only has an 8 bit address bus!

Here's the trick: your 9th bit (bit 8, counting from 0) of the address bus (coming from your CPU) will be connected to the chip enables of the two RAM chips.

  • Chip 0's CE will be connected to address bit 8 through a NOT gate. That means that when the bit 8 of the address is low, the chip enable pin is activated, and the chip is enabled. The other address bus bits are connected as normal. The chip only sees the addresses as ranging from 0 to 255 as before, and works normally.
  • Chip 1's CE will be connected directly to address bit 8. That means that when the bit 8 of the address is high, the chip enable pin is activated, and the chip is enabled. The other address bus bits are connected as normal. The chip only sees the addresses as ranging from 0 to 255 as before, and works normally.

In effect, bit 8 picks which of the two memory chips is addressed. The other 8 pins pick which cell within the active chip is being read/written.

  • You can think of chip 0 as being "mounted" on bits 0b0_0000_0000-0b0_1111_1111 of the CPU's address space
  • You can think of chip 1 as being "mounted" on addresses 0b1_0000_0000-0b1_1111_1111 of the CPU's address space.

As you see, memory addresses are nothing more than a set of values on an address bus of each chip. They're not unique, but overlapping address bus values are possible by using chip enable pins to only ever select one of the chips.

You can imagine a scaled up version of this. You might have two memory chips, each with a capacity of 65,536 bytes (meaning they have at least a 16 bit address bus). You can use two bits of address bus to address one of 4 chips (00, 01, 10, 11, using a 2-to-4 de-multiplexer), and 16 bits of address space fed directly to the chip. You would end up with:

  • Chip 0, mounted on address space 0b00_0000_0000_0000_0000-0b00_1111_1111_1111_111
  • Chip 1, mounted on address space 0b01_0000_0000_0000_0000-0b01_1111_1111_1111_111
  • Chip 2, mounted on address space 0b10_0000_0000_0000_0000-0b10_1111_1111_1111_111
  • Chip 2, mounted on address space 0b11_0000_0000_0000_0000-0b11_1111_1111_1111_111

And just like that, now you have a computer with 256k of RAM, using only 65k RAM chips.

  • Thank you for clarifying that, I wasn't sure if RAM blocks had a fixed address like as you say an IP. I do understand that the entire size of RAM is addressed, dependant on the address bus length I think, but really I think that's what my question is, what is giving the addresses from the first byte to the very last. What is happening before the BIOS is loaded, where the memory has a sort of address map. Again thank you very much for the question, loved the detail you wrote too!
    – jdow
    Apr 23, 2021 at 19:42
  • Also, would the RAM be addresses hierarchically, where as you say byte 0 has the lowest address, and the last byte has the largest?
    – jdow
    Apr 23, 2021 at 19:49
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    "Also, would the RAM be addresses hierarchically" I don't know what you mean by 'hierarchically", but this: "where as you say byte 0 has the lowest address, and the last byte has the largest?" isn't hierarchical. | That statement is tautological. "say byte 0 has the lowest address" -> Yes, since there's no counting number smaller than 0, it's literally impossible for it to be any other way. | "and the last byte has the largest?" -> That's just the definition of "last"
    – Alexander
    Apr 23, 2021 at 20:01
  • "What is happening before the BIOS is loaded, where the memory has a sort of address map." I'm not too familiar with BIOS at the low level, but I am quite familiar with the lower-level hardware below that. The address mapping I describe in my answer is a fixed mapped that's determined by the actuality of the circuit. On modern systems, it's more complicated (e.g. each DDR* ram stick has its own chip id lines, rather than a singular chip enable), but I don't know much about those details.
    – Alexander
    Apr 23, 2021 at 20:05
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    No no, doesn't sound stupid! it's just hard to talk about details things like this over text, especially given the char limit. "so each byte has a randomly assigned address" "each byte" isn't a thing. Bytes aren't cars, assigned to one parking space or another. By that analogy, the byte IS the parking space. There is a byte at address 0. There is another byte at address 1. There is yet another byte at address 2, ... and so on. When you store some data, you copy 1 byte of data from the source location, to the desired destination. Your OS is free to pick that dest address as it pleases
    – Alexander
    Apr 23, 2021 at 21:19

A memory unit is built from memory cells (storing one byte each) and a tree of logic gates which are basically small switches. An address is a set of bits which indicate to the switches which memory cell to read or update.

                │    ┊  └───[byte]    
CPU <-->  [switch]   ┊  
             ┊  │       ┌───[byte]
             ┊  └─[switch]
             ┊       ┊  └───[byte]  
             ┊       ┊ 
Address:    bit0    bit1

Above is an illustration showing how one out of four memory cells connected by switches can be selected by two bits. So the two bits 00 you get the first byte, 01 you get the second byte and so forth.

You just need one additional switch any time you double the amount of memory, so with 3 bit you can address 8 bytes, 4 bits give you 16 bytes, and 16 bits give you 65,536 bytes.

So an address is just a set of bits which correspond to a chain of switches which gets us to a specific memory cell. A set of bits can also be interpreted as an integer number, and we call that number the address of the memory cells.

In other words, a memory cell does not really get the address assigned. Rather, the address follows logically from where the cell is located in the hierarchy of switches.

Of course this gets a lot more complicated on modern processors where there are multiple levels of caches, virtual memory mapping into physical memory and so forth. But fundamentally an address is just a set of bits corresponding to a set of switches which lets us select a specific memory cell.

  • Okay, thank you for the answer. So my understanding from that is, the memory address is actually sort of the amount of switches which must be travelled though to access the byte? Would that also mean that the more complex the circuitry within the RAM ie higher capacity DIMMS, the larger the address?
    – jdow
    Apr 23, 2021 at 19:56
  • @jdow exactly, the higher the capacity the longer the address. Using x bits you can address 2^x cells.
    – ciamej
    Apr 24, 2021 at 14:00
  • @jdow Yes, your computer doesn't actually have 64-bit addresses inside it. Your computer has perhaps 35-bit addresses (8GB), and the other 29 bits don't go anywhere. Some of them don't go out of the CPU; some of them go out of the CPU but don't go anywhere on the motherboard. Also I think the CPU knows this and won't let you use those bits.
    – user253751
    Apr 24, 2021 at 18:30

A RAM element is an electric circuit with data and address input lines. The spec that it implements goes roughly like this:

If you select a specific pattern of address inputs in write mode, then the same pattern of data inputs will be produced as output on the data lines if you select the same pattern on the address inputs in read mode (as long as you keep delivering power to the element).

So the fact that a collection of bits (e.g. a byte) is stored in a specific part of the chip is encoded into the physical layout of the chip.

Now, viewed as an electric circuit, the RAM chip is basically a pattern repeater. What you do with this capability is a question for compilers and operating systems. Typically, a compiler will see a variable declaration and choose an address for that variable; for instance, it might know that the data segment starts at address 10000, we've already used 412 bytes for other variables, so everywhere this next variable is referenced, it'll insert the address 10412 (binary pattern 0010100010101100) into the generated machine code.

Obviously, OS and compiler construction is vastly more complicated than this, but the principles don't actually change very much in real life.

  • Thank you for the answer, I really appreciate it. Would I be right in saying that the memory addresses are assigned during manufacture of the RAM chips? If so wouldn't that mean that there is a possibility of two RAM chips having the same address?
    – jdow
    Apr 23, 2021 at 10:22
  • Correct. One of the complications is that multiple RAM chips in one computer have to be integrated onto the same motherboard in some way, and that means having additional lines on the address bus that distinguish the chip in addition to distinguishing the byte within a chip. This is roughly comparable to telephone area codes. The memory subsystem of a modern computer is a fascinating field of study all by itself. Apr 23, 2021 at 10:36
  • Okay, so its a possibility multiple chips can have the same address. So how are they distinguished? Also, how would the computer know the addresses, does it make a massive request during boot up, or what's going on? Thank you again for your answer.
    – jdow
    Apr 23, 2021 at 10:43
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    @jdow It is not just possible, it is expected that all memory chips from a specific design will have the same address. Not only that, the vast majority of memory chips every manufactured expect to receive addresses from 0 to the size of the chip. It is the responsibility of the memory controller and all the motherboard interface circuitry to select the correct chip and translate the addresses based on the upper bits. Apr 23, 2021 at 14:01
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    @jdow: no, this has nothing to do with virtual memory. As user1937198 wrote, It is the responsibility of the memory controller and all the motherboard interface circuitry to select the correct chip and translate the addresses based on the upper bits - so lets say there your PC contains 4 memory chips each one with 1GB of memory byte cells, that means 2^30 bytes per chip. When a 32 bit CPU generates an adress signal, the adress bits 0 to 29 will determine the adress within a chip, and the adress bits 30 to 31 will determine which chip will get adressed.
    – Doc Brown
    Apr 23, 2021 at 14:34

In short, it up to the memory controller to detect DRAM and create physical address map. The process is under the assist from BIOS code. The address map may be very complex by interleaving different channel and bank. you can read this material: https://web.eic.nctu.edu.tw/lpsoc/courses/MS2017Spring/supplemental/5.%20DRAM%20Memory%20Controller%20.pdf

from https://wiki.osdev.org/Detecting_Memory_(x86) :

"How does the BIOS detect RAM? I'll just do it that way." Unfortunately, the answer is disappointing: Most BIOSes can't use any RAM until they detect the type of RAM installed, then detect the size of each memory module, then configure the chipset to use the detected RAM. All of this depends on chipset specific methods, and is usually documented in the datasheets for the memory controller (northbridge). The RAM is unusable for running programs during this process. The BIOS initially is running from ROM, so it can play the necessary games with the RAM chips. But it is completely impossible to do this from inside any other program.

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