Reading from the other answers, I think one of misunderstandings you're operating under is that memory addresses are somehow globally unique, like IP addresses, MAC addresses, or phone numbers. That's not the case.
Fundamentally, a RAM chip just has the following things:
- Some number of address lines, called the address bus
- (this determines the maximal number of addressable words within the chip)
- Some number of data lines, called the "data bus"
- (this determines the size of a word, the size of data that can be read from a single address)
- A "write enable" (WE) pin
- When enabled, pulsing the clock will cause the value of the addressed memory cell to be set to the value read from the data bus
- When disabled, pulsing the clock will cause the value of the data bus to be set to the value read out from the addressed memory cell
- A clock pin. When pulsed, the value of the address bus is read/written, depending on the WE pin
- A "chip enable" (CE) pin, which either makes the chip enabled, or not.
When enabled, the chip operates as described
When disabled, the data bus is set to a 'high impedance' state.
This is critical. It allows multiple chips to share the same data bus. Consider what would happen in this example: bit 0 of chip 0's databus might be low, while bit 0 of chip 1 is high (e.g. 5V). Since chip 0 and chip 1 share a databus, their two data bit 0 pins are connected together. If they have different values, such as the case here, you have 5V connected to 0V. This is a short circuit, and the magic smoke will appear.
Using the chip enable pins, you can have it so that disabled chips effectively "disconnect" themselves from the rest of the circuit. So long as only one of the chips is active at a time, then there is only one chip connected to the databus, and thus no shorts will happen.
You can imagine a 256 byte RAM chip. Addressing 256 values means that the address space of this chip ranges from
0b0000_0000 (0) to
0b1111_1111 (255). But what if you want to have a computer with 512 bytes of RAM, but there are no 512 byte chips in production?
Well, you can use two 256 RAM chips, together! Each one has 256 byte-sized memory cells, with their own 8 bit buses that accept values from 0 to 255. Now, notice that addressing 512 bytes would need a memory space ranging from
0b0_0000_0000 (0) to
0b1_1111_1111 (511). This needs a 9 bit address bus. But each of our chips only has an 8 bit address bus!
Here's the trick: your 9th bit (bit 8, counting from 0) of the address bus (coming from your CPU) will be connected to the chip enables of the two RAM chips.
- Chip 0's CE will be connected to address bit 8 through a NOT gate. That means that when the bit 8 of the address is low, the chip enable pin is activated, and the chip is enabled. The other address bus bits are connected as normal. The chip only sees the addresses as ranging from 0 to 255 as before, and works normally.
- Chip 1's CE will be connected directly to address bit 8. That means that when the bit 8 of the address is high, the chip enable pin is activated, and the chip is enabled. The other address bus bits are connected as normal. The chip only sees the addresses as ranging from 0 to 255 as before, and works normally.
In effect, bit 8 picks which of the two memory chips is addressed. The other 8 pins pick which cell within the active chip is being read/written.
- You can think of chip 0 as being "mounted" on bits
0b0_1111_1111 of the CPU's address space
- You can think of chip 1 as being "mounted" on addresses
0b1_1111_1111 of the CPU's address space.
As you see, memory addresses are nothing more than a set of values on an address bus of each chip. They're not unique, but overlapping address bus values are possible by using chip enable pins to only ever select one of the chips.
You can imagine a scaled up version of this. You might have two memory chips, each with a capacity of 65,536 bytes (meaning they have at least a 16 bit address bus). You can use two bits of address bus to address one of 4 chips (
11, using a 2-to-4 de-multiplexer), and 16 bits of address space fed directly to the chip. You would end up with:
- Chip 0, mounted on address space
- Chip 1, mounted on address space
- Chip 2, mounted on address space
- Chip 2, mounted on address space
And just like that, now you have a computer with 256k of RAM, using only 65k RAM chips.