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If an I/O device is reading the main memory (directly) then is it possible for the CPU to access the cache?

I think it's possible for the CPU to access the cache in case of a hit. But in case of a miss there could be two scenarios.

  1. Either the CPU pauses the DMA and fetches blocks from the main memory (haven't heard of DMA being interrupted), Or,
  2. The CPU waits for the DMA to complete

Which is it?

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Without miss, no problem. With a miss that can be filled from L2 or L3 cache, no problem. High end CPUs can have two paths to separate RAM chips, so they could run simultaneously. CPU and external hardware or multiple CPUs accessing the same RAM chip someone would have to wait.

If hardware designers determine that this causes a slowdown, it could be possible that RAM could be designed to have multiple accesses queued up to run faster.

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  • Thank you for clarifying this!
    – Mugen
    May 23 at 17:22

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