Questions tagged [cpu]
CPU is the abbreviation for central processing unit. Sometimes referred to simply as the central processor, but more commonly called processor
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How did old OSs create or expand a segment in memory without issues?
On an 8086 CPU before the flat memory model had been adopted, when the OS wanted to create a new segment for a process, how did it know what virtual memory ranges were already covered by existing ...
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3answers
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How to align on both word size and cache lines in x86
From what it sounds like, a 64 bit processor means aligning to 64 bits, which means if you have unicode utf-8 stored in there, each 8-bit chunk would take up 64 bits of space. That doesn't really make ...
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two processes with same execute time [closed]
Process A take 10 seconds to finish an execution.
Process B take 10 seconds to finish an execution.
Is it possible to take 5, 8, 15 seconds to finish an execeution if they run stimulately.
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What is more efficient: Reading and parsing a large JSON file, or large CSV file?
I plan on using Scrapy to crawl a local website for a LOT of data and store it in a file. Then I plan to parse that file and put some of the data in a SQL database.
Will my computer use less CPU and ...
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4answers
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Does instruction length affect cycles per instruction?
ISAs define things like instruction lengths and the instructions themselves and there are some things that I do not understand.
Does the instruction length (the amount of bits) affect the amount of ...
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1answer
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What receives the output of the ALU?
I know that the Arithmetic Logic Unit (ALU of a processor performs arithmetic (and bitwise) operations and the result is stored as the ALU's output - but what component, device or software is actually ...
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2answers
684 views
How does a CPU load multiple bytes at once if memory is byte addressed?
I've been reading about CPUs and how they are implemented, and some big complex architectures (looking at you x86) have instructions that load from memory during one clock cycle. Since one address ...
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Large inlined stream of instruction: cache problems?
[ARM64]
Context:
I have a 800Mb worth of assembly code. I use contiguous TLB bit to manage to reach pages with up to 1Gb with no page miss issue.
It is the only app running on this board.
That ...
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2answers
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Increase processing use of Digital Signal Processor
I have a DSP (Digital Signal Processor) with a very well defined application, (this explication will be simplified)
The DSP uses TDM (Time Division Multiplexer) frames to receive audio information, ...
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3answers
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What does “address space” means when talking about IO devices?
The following quote is from this page:
While some CPU manufacturers implement a single address space in their
chips, others decided that peripheral devices are different from
memory and, ...
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1answer
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What does “data bus control” mean?
This video mentions the following:
What does it mean for the DMA controller to be granted the data bus control, does that mean the CPU cannot use the bus to access memory and IO devices until the DMA ...
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3answers
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What happens to multiple parallel tasks running on a server when CPU hits 100% usage?
I am running 10 instances of the same executable where each executable is accessing a different 1/10 chunk of the total data that needs to be processed on a Windows Server 2012 R2. (Intel(R) Xeon(R) 2....
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558 views
Feature of CPU needed to run Javascript fast
This is more of a Computer Engineering question, but what is the feature of a CPU to run Javascript fast? I use to access the internet with an AMD Phenom II with 6 cores and I could almost have as ...
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3answers
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How does a single thread run on multiple cores?
I am trying to understand, at a high-level, how single threads run across multiple cores. Below is my best understanding. I do not believe it is correct though.
Based on my reading of Hyper-threading,...
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2answers
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Why are CPUs' datapaths mutiple of 8?
Current and common processing units are 8, 16, 32, 64, 128, etc bit. Why are their datapath multiple of 8 ? Is this all linked to the fact that the industry has settled with a 8-bit byte ?
The PDP-7 ...
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2answers
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Separate Thread Pools for I/O and CPU Tasks
I've been puzzling over a good implementation for this for a while. I have a program that does a long-running I/O operation (downloading a file) and a long-running CPU operation (parsing its contents)...
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2answers
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How to maximize the CPU usage of a Python subprocess?
I have a Python script launching a C++ executable.
The C++ executable is a multithreaded program that usually takes several hours to run. The way the C++ code is written, it will run on all the ...
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3answers
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Why do compilers typically only generate executables for the platform they are installed on?
I'm a C++ developer and in an attempt to better understand cross-platform development, I'm trying to get a better understanding of some implementation details of compilers and how exactly they create ...
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4answers
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The difference between accumulator-based and register-based CPU architecture?
I don't understand the difference between an accumulator-based CPU architecture and a register-based CPU architecture. I know x86 is register-based but it has an accumulator-like register. I only ever ...
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2answers
225 views
How to calculate how much of the CPU is used?
Say we have an interrupt that is generated once each time that 1024 bytes of network traffic arrives. Each interrupt takes 3.5 microseconds to process and the network speed is 100Mb.We want the ...
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4answers
270 views
Is it possible for a computer system to have constant/zero CPU load?
For example, a simple program in a simulated environment that waits for user input seems to be doing no work, so I guess it uses CPU only for the time.
I'd like to know if computer systems (that don'...
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3answers
359 views
Why can less precise data like float be faster than larger, more precise data like double?
I am currently reading a chapter in a textbook on Processor Architecture and saw the following statement:
The less precision there is, the less space is occupied by a program variable in memory. ...
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2answers
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How does the web application support 150 max threads when the cpu only supports 2? [duplicate]
doing an lscpu cmd this is what i get
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 2
On-line CPU(s) list: ...
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1answer
268 views
How is the data path controlled between ALU and registers?
On some machines the operation of data path between ALU and registers is controlled by microprogram . On some machines , it is controlled by
hardware .On machines with software control of the data ...
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4answers
524 views
When it is worth it to spend RAM for computational speed? [closed]
I am developing data analytics algorithms that are supposed to process large amounts of data.
Thus I am aiming to develop my mathematics already in such a way that it is possible to distribute the ...
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3answers
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Source of loading value to the register or memory location
When we load a register or memory location with a value (e.g. MVI 3A or MVI 53), what initializes register or memory location with that specific value? It is the CPU who performs the initialization, ...
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2answers
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How to wait for a certain amount of time if time functions are not reliable [closed]
How can I manage my code to exactly wait for a certain amount of time (say 10s), if all * time functions on the system are not reliable and return immediately ?
Sleep(10000); // Do not sleep for 10s ...
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2answers
191 views
How can an interpreter produce output of some code, without having the computing components like ALU of a processor?
I have gone through lot of explanations about a compiler and interpreter. I think I understood the difference between compiler and interpreter clearly. I'll explain my learning through the following ...
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1answer
174 views
Is CPU only task executer in microprocessor?
I was wondering if are all tasks executed by the CPU (fetching, reading, writing, etc.)? Everything is controlled, manipulated or executed by the CPU?
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How does sleeping a thread work?
When you sleep a thread, what is actually going on?
I see that sleeping a thread "pauses the current thread for a given period of time". But just how does it work?
According to How Thread.sleep() ...
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3answers
392 views
Is it possible and faster to run an application on an unused CPU core?
Is it possible to move an application (or task) to another core to make it run faster and get all of that cores processing power?
The way I understand it is that in an operating system applications ...
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7answers
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In software programming, would it be possible to have both CPU and GPU loads at 100%?
This is a general question on a subject I've found interesting as a gamer: CPU/GPU bottlenecks and programming. If I'm not mistaken, I've come to understand that both CPU and GPU calculate stuff, but ...
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4answers
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Byte addressable vs bit addressable
Why are most computers byte addressable instead of bit addressable?
By B/b addressable I mean that processor can operate on level of single B/b.
Bit addressable advantages:
Booleans have size of ...
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3answers
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Operation excution in terms of clock cycles
Typically for a single instrcution, 6 machine cycles are needed:
FETCH instruction
DECODE instruction
EVALUATE ADDRESS
fetch OPERANDS
EXECUTE oepration
STORE result
My concern is regarding the fifth ...
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1answer
157 views
What was the first mass-produced CPU to have an instruction for multiplication?
The CPU I am most familiar with is the Z80 which was first released in 1976. The most complicated mathematical single instructions it has are integer ADD, SUB and closely related instructions, such as ...
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3answers
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Are there CPUs that perform this possible L1 cache write optimization?
When the CPU with an L1 cache does a write, what normally happens is that (assuming that the cache line that it is writing to is already in the L1 cache) the cache (in addition to updating the data) ...
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0answers
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Handling exceptions in multiple-issue CPUs
From what I read, VLIWs execute instructions in bundles, i.e. the CPU loads a bundle of instructions and dispatches them all at once. This is possible because the compiler scheduled instructions in ...
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2answers
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What could “move an instruction without a 16-bit bus” mean?
Spoiler alert! This question (and, possibly, answers) could contain spoilers regarding "Halt and Catch Fire" TV series.
Background
I'm a web deleloper and do not have a CS degreee, so my ...
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3answers
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Which programming language is used to write a BIOS program?
As I understand, the BIOS code/bitstream that is held in the ROM should be generic (work alongside with multiple CPU types or ISAs). In addition, I saw mentioned on the web that it is possible to dump ...
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Cost of cache coherency/sharing data across multiple cores?
If I have two CPU cores, one is writing a particular cache line and the other core wishes to
Read
Write
the same cache line, what are the costs (in cycles) for doing so?
I am a little unsure ...
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6answers
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Why do we have to wait for I/O?
It's always been known that Disk operations are slow and we know the reasons why they are slow.
So the question here is why do we have to wait for I/O or why is there such a thing as IOWait, etc.?
I ...
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3answers
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Pre-calculate values or not on Raspberry Pi
Say that you want to rotate something 360 steps 100 times. You now have a choise to pre-calculate 360 sin and cos values once and then use the stored values 100 times, or you can calculate sin and cos ...
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2answers
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What is a latency-bound and a memory-bound application in HPC?
I understand that in HPC hybrid systems, for instance a MIC architecture, main memory access is much slower than access to data in own cache or in the cache of another core.
I read that HPC MIC ...
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1answer
392 views
Relationship of common MCUs/CPUs to FPGA and ASIC
I'm trying to understand the relationship between "common" MCUs/CPUs such as Intel, AMD, PowerPC, AVR, ARM, etc. and FPGAs and ASICs.
Here is my understanding:
These commons MCUs/CPUs (again, Intel, ...
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2answers
790 views
Compiling and deploying a C program to an MCU running an RTOS
Please note: Even though I'm specifically talking about an RTOS called Embox here, and even though I'm talking about AVR/ARm, I think this question can be answered by anybody whose ever done a fair ...
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1answer
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Compiling and deploying RTOS to an MCU
Please note: Even though I'm specifically talking about an RTOS called Embox here, and even though I'm talking about AVR/ARm, I think this question can be answered by anybody whose ever done a fair ...
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1answer
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How does a program talk to a graphics card?
I have heard that GPU's are better at performing certain tasks than a CPU. My question is, how does a program tell a graphics card to process something instead of the CPU? Does the program talk to the ...
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1answer
543 views
Translation Lookaside buffer - Lookup By Page Size
I am having a hard time finding documentation that explains precisely how the various TLB caches are used in modern processors.
Most modern processors have separate TLBs for code/data. That in itself ...
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0answers
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What parallelism happens in a vector processor?
From Tanebaum's Structured Computer Organization
A vector processor is very efficient at executing a sequence of
operations on pairs of data elements. All of the operations are
performed in a ...
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2answers
771 views
What does “issue or start an instruction” mean?
From Section 2.1.3 RISC vs CISC from Structured Computer Organization by Tanenbaum,
While the initial emphasis was on simple instructions that could be
executed quickly, it was soon realized ...
