69

A variable is a logical construct that goes to the intent of an algorithm, whereas a memory location is a physical construct that describes the operation of a computer.  Generally speaking, in order to execute a program there is (compiler generated) mapping between the logical notion of a variable and the storage of the computer. (Even in assembly ...


49

A (somewhat) popular alternative to a call stack are continuations. The Parrot VM is continuation-based, for example. It is completely stackless: data is kept in registers (like Dalvik or the LuaVM, Parrot is register-based), and control-flow is represented with continuations (unlike Dalvik or the LuaVM, which have a call stack). Another popular data ...


35

In the olden days, processors didn't have stack instructions, and programming languages didn't support recursion. Over time, more and more languages choose to support recursion, and hardware followed suite with stack frame allocation capabilities. This support has varied greatly over the years with different processors. Some processors adopted stack frame ...


26

Intel had 5 pipeline stages in its original Pentium architecture. The number of stages peaked at 31 in the Prescott family, but decreased after that. Today, in the Core series II processors (i3, i5, and i7), there are 14 stages in the processor pipeline. Microarchitecture Pipeline stages P5 (Pentium) 5 P6 (Pentium 3) 10 P6 (Pentium ...


25

I'd argue that it's not so much won as ceased to matter. ARM which makes up basically all of the mobile market is bi-endian (oh, the heresy!). In the sense that x86 basically "won" the desktop market I suppose you could say that little endian won but I think given the overall code depth (shallow) and abstraction (lots) of many of today's applications, it's ...


20

Is it safe to say that a variable is the same thing as a memory location? No. Variable and memory location are two abstractions at two different abstraction levels. Variable and pointers are higher level concept at the code/language level, memory location is a lower level concept at the machine level. Once a code had been compiled into an executable, there'...


17

How does understanding physics help people drive a car? They understand phenomena like brake fade, and will compensate for it. They understand center of gravity and how tires grip the road. They understand hydroplaning, and how to avoid it. They know how to best enter and exit a curve. They are far less likely to tailgate. And so on. You can drive a car ...


16

Variables are language constructs. They have a name, reside within a scope, may be referenced by other parts of the code, etc. They are a logical entity. The compiler is free to implement this language construct in any way it pleases, as long as the observable behavior is that prescribed by the language standard. As such, the variable does not even need to ...


14

You need log2(n) bits to address n bytes. For example, you can store 256 different values in an 8 bit number, so 8 bits can address 256 bytes. 210 = 1024, so you need 10 bits to address every byte in a kilobyte. Likewise, you need 20 bits to address every byte in a megabyte, and 30 bits to address every byte in a gigabyte. 232 = 4294967296, which is the ...


14

TL;DR Call stack as a function call mechanism: Is typically simulated by hardware but is not fundamental to the construction of hardware Is fundamental to imperative programming Is not fundamental to functional programming Stack as an abstraction of "last-in, first-out" (LIFO) is fundamental to computer science, algorithms, and even some non-technical ...


13

Your computer is a von Neumann machine. All general purpose computers are. The only exceptions are specialized co-processors like GPUs. It's not that you can't have a Harvard machine (or any other architecture). It's just that nobody builds them, especially not for sale (modulo co-processors, of course).


11

No, not necessarily. Read Appel's old paper Garbage Collection can be faster than Stack Allocation. It uses continuation passing style and shows a stackless implementation. Notice also that old computer architectures (e.g. IBM/360) did not have any hardware stack register. But the OS and compiler reserved a register for the stack pointer by convention (...


10

You've got some good answers so far; let me give you an impractical but highly educational example of how you could design a language without the notion of stacks or "control flow" at all. Here's a program that determines factorials: function f(i) => if i == 0 then 1 else i * f(i - 1) let x = f(3) We put this program in a string, and we evaluate the ...


10

How did heavy software in the early days managed to run on 4MB RAM computer? It wasn't heavy. That's it. There is no magic to it. Your question is based on a false premise. I remember that my mom was using my dad's old IBM PC/AT with 512 KiByte of RAM and a 20 MiByte HDD well into the 1990s for word processing using Volkswriter and then later StarWriter. ...


9

Could anyone give an overview of how list structures which are composed of a head and a tail which references the rest of the list i.e linked list are represented in memory of the computer? In a naive implementation, each node is allocated separately, so the nodes would be spread more or less randomly through the heap memory, wherever the memory allocator ...


8

The MIPS architecture is derived from an architecture specifically designed at Stanford for educational use and for research into CPU ISAs and architectural implementations. Early academic RISC architecture were designed such that they could be implemented (included layout) by small teams of graduate or upper-division students (not the cast of thousands ...


8

Regarding other modern processors: ARM up to 7: 3 stages (still widely used is simpler devices) ARM 8-9: 5 stages; ARM 11: 8 stages; Cortex A7: 8-10 stages; Cortex A8: 13 stages; Cortex A15: 15-25 stages. From Wikipedia.


8

You might want to step back and see where and why those existing models come from. When a process is created, it is simply given a flat storage area which is simply indexed from 0 to N. Because this storage area (talking about RAM here) is backed by a dedicated hardware and some fancy semiconductors it happens to be pretty fast, but it's not the only one of ...


8

A register-based CPU architecture has one or more general purpose registers (where "general purpose register" excludes special purpose registers, like stack pointer and instruction pointer). An accumulator-based CPU architecture is a register-based CPU architecture that only has one general purpose register (the accumulator). The main advantage/s of "more ...


8

Yes. The DMA controller takes ownership of the bus for the duration of the transfer. That said, I feel obliged to point out that at least on PC-based machines, DMA controllers have been almost entirely obsolete for quite a while now. On a reasonably modern machine, the DMA controller is used only for I/O to/from floppy disks (and only "directly" connected ...


7

Intel and AMD have a large share of the Desktop market. Other processor families are much more common in devices outside that fairly small area of influence. MIPS is also a RISC architecture which are generally thought of as being easier to learn. You learn a small number of commands that can be combined orthogonally a multitude of ways similar to UNIX style ...


7

This really all depends on how you are defining a CPU. If you are talking about the embedded CPUs found in many of the devices you use, then yes, they often contain both the RAM and the processing units that would make up a common computer. If you are talking about a CPU that you would find in a consumer desktop/laptop you would see that the cache you are ...


6

Well, there are instructions that don't access the data cache, but it's impossible to access the data cache without using an instruction, so by definition the instruction cache is used more often. If you're talking about which one has fewer cache misses, that's going to be highly program specific. A tight loop that accesses a gigabyte of memory will have ...


6

Most current general purpose CPUs use Modified Harvard Architecture. The CPU cores can access program and data independently in their separate L1 caches. At the outside, there are no separate program and data memories (nor the other cache levels are separated). Could there be another architecture or are these architectures the only ones known? All the ...


6

Existing answers have explained that the formula for addressing ram is 2^BITS = Addressable ram, but have not explained why. Consider a system with 2 bits. It can address 4 bytes of ram as follows: Byte 0: 00 Byte 1: 01 Byte 2: 10 Byte 3: 11 For each additional bit, we can address twice as much memory. E.g., add a 0 bit to each for bytes 0-3, then add ...


6

So basically you access the device controller registers through memory. Not exactly, which is why the diagram in the question doesn't quite depict memory-mapped I/O. Memory-mapped I/O uses the same mechanism as memory to communicate with the processor, but not the system's RAM. The idea behind memory mapping is that a device will be connected to the ...


5

I don't know how much the designers of the ARM architecture took inspiration from the PDP-11. They probably knew the PDP-11 architecture well as it was one of the major CPUs of the 1970s. However, it's more the x86 which is different from the other two. ARM is a RISC architecture: its instructions tend to follow a few model and to do just one thing. Compare ...


5

For integers, the only exponentiation operations that are normally present in hardware are the shifts, << and >> (in C parlance), which multiply by exponential powers of two. For anything else with integers, you run out of bits to represent things far too quickly for it to be useful; by the time you've sorted that problem out, you might as well ...


5

Short answer: because it is the default approximation of a real number the language in question provides.


5

The exponent is unsigned. It cannot be -1. The smallest it can be is 0, which translates to 2^-127. You might ask then, "If so, how is 2^-128 represented in single precision?!". The answer lies in normalization. Usually numbers are normalized (i.e. multiplied by a power of 2) so that the leading bit of their mantissa is 1. That bit can then be omitted,...


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