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103

BIOSes used to be written exclusively in assembly language, but the transition was made a long time ago to write the majority of the code in some higher level language, and leave written in assembly as few portions of it as possible, preferably only the bootstrapper, (the very first few hundreds of instructions that the CPU jumps to after a start / reset,) ...


84

The operating system offers time slices of CPU to threads that are eligible to run. If there is only one core, then the operating system schedules the most eligible thread to run on that core for a time slice. After a time slice is completed, or when the running thread blocks on IO, or when the processor is interrupted by external events, the operating ...


82

Every processor I've worked on does comparison by subtracting one of the operands from the other, discarding the result and leaving the processor's flags (zero, negative, etc.) alone. Because subtraction is done as a single operation, the contents of the operands don't matter. The best way to answer the question for sure is to compile your code into ...


62

Theoretically yes, but practically it's rarely worth it. Both CPUs and GPUs are turing-complete, so any algorithm which can be calculated by one can also be calculated by the other. The question is how fast and how convenient. While the GPU excels at doing the same simple calculations on many data-points of a large dataset, the CPU is better at more ...


61

They're not quite the same. The registers are the places where the values that the CPU is actually working on are located. The CPU design is such that it is only able to actually modify or otherwise act on a value when it is in a register. So registers can work logic, whereas memory (including cache) can only hold values the CPU reads from and writes to. ...


59

If cooling is insufficient, the CPU might overheat. But they all (well, at least all modern PC CPUs) feature various thermal protection mechanisms which will throttle the clock speed or, as a final resort, shut down. So yes, on a dusty laptop, 100 % CPU load could cause temporary problems, but nothing will break or "degrade" (whatever that means). For CPU ...


47

If the code says A = A + 1 compiled code does this add A, 1 interpreted code does this (or some variation) look up the location of A in the symbol table find the value of A see that 1 is a constant get its value add the value of A and the value of 1 look up the location of A in the symbol table store the new value of A get the idea?


45

It may be possible to do this "by accident" with careless use of core affinity. Consider the following pseudocode: start a thread in that thread, find out which core it is running on set its CPU affinity to that core start doing something computationally intensive / loop forever If you start four of those on a two-core CPU, then either something goes wrong ...


37

Executables do depend on both the OS and the CPU: Instruction Set: The binary instructions in the executable are decoded by the CPU according to some instruction set. Most consumer CPUs support the x86 (“32bit”) and/or AMD64 (“64bit”) instruction sets. A program can be compiled for either of these instruction sets, but not both. There are extensions to ...


36

It is not related to game programming. Some scientific code can also use both the GPU and the CPU. With careful -and painful- programming, e.g. by using OpenCL or CUDA, you could load both your GPU and your CPU near 100%. Very probably you'll need to write different pieces of code for the GPU (so called "kernel" code) and for the CPU, and some boring glue ...


34

It could be necessary to have 4 cores because the application runs four tasks in parallel threads and expects them to finish almost simultaneously. When every thread is executed by a separate core and all threads have the exact same computational workload, they are quite likely (but far from guaranteed) to finish roughly the same time. But when two threads ...


28

CPU (its memory controller specifically) can take advantage of the fact that the memory is not mutated Advantage is, this fact saves compiler from using membar instructions when data is accessed. A memory barrier, also known as a membar, memory fence or fence instruction, is a type of barrier instruction which causes a central processing unit (CPU) or ...


26

Intel had 5 pipeline stages in its original Pentium architecture. The number of stages peaked at 31 in the Prescott family, but decreased after that. Today, in the Core series II processors (i3, i5, and i7), there are 14 stages in the processor pipeline. Microarchitecture Pipeline stages P5 (Pentium) 5 P6 (Pentium 3) 10 P6 (Pentium ...


25

Is there a difference in performance on the ALU level in comparisons between very large numbers vs very small ones? It's very unlikely, unless going from a small number to a large number changes your numeric type, say from an int to a long. Even then, the difference might not be significant. You're more likely to see a difference if your programming ...


24

It's possible to write asynchronous IO where you tell the OS to dispatch a disk read/write and then go do something else and then later check if it's done. It's far from new. An older method is using another thread for the IO. However that requires that you have something to do while that read is being executed and you will not be allowed to touch the ...


24

There is no such thing as a single thread running on multiple cores simultaneously. It doesn't mean, however, that instructions from one thread cannot be executed in parallel. There are mechanisms called instruction pipelining and out-of-order execution that allow it. Each core has a lot of redundant resources that are not utilized by simple instructions, ...


22

This multiplication algorithm does not replace multiplication with addition. Instead, it splits the multiplication into a number of smaller multiplications that are easier for humans to understand. Humans (unlike computers) deal well with patterns and symbols, less so with large numbers (where “large“ means “multiple digits”). 321 × 254 × | 2E2 + 5E1 + ...


22

summary: Finding and exploiting the (instruction-level) parallelism in a single-threaded program is done purely in hardware, by the CPU core it's running on. And only over a window of a couple hundred instructions, not large-scale reordering. Single-threaded programs get no benefit from multi-core CPUs, except that other things can run on the other cores ...


21

I believe it comes from the very early days of computing, when memory was very limited, and it was not wise to pre-allocate a large chunk of memory for exclusive use by the stack. So, by allocating heap memory from address zero upwards, and stack memory from the end of the memory downwards, you could have both the heap and the stack share the same area of ...


19

No, instruction sets aren't "standardized" in a way that you could produce assembly that's fit for – or is simply mappable to – ARM, x86, PPC, MIPS, Itanium, Sparc, ... (and their variants). Native code compilers are pretty complex beasts. Not all the work they do is processor-specific. All the lexing/parsing is language-dependent but not chip-...


19

Many processors have "small" instructions which can perform arithmetic operations, including comparisons, on certain immediately-specified operands. Operands other than those special values must either use a larger instruction format or, in some cases, must use a "load value from memory" instruction. In the ARM Cortex-M3 instruction set, for example, there ...


19

The I/O schemes you are describing are in current use in computers. why the CPU actually has to stay there, practically not doing anything else than just waiting for IO? This is the simplest possible I/O method: programmed I/O. Many embedded systems and low/end microprocessors have only a single input instruction and a single output instruction. The ...


17

what makes it difficult for say the visual C++ compiler on windows to generate a linux binary executable file? Other than an unwillingness to do that on Microsoft's part, absolutely nothing. The obstacles aren't technical. Development toolchains are just programs that take input and produce output. Visual C++ produces x86 assembly and then uses an ...


16

First if you are concerned about recent (last 5-10 years, since Nahalem?) Intel x86 architecture, then you're a little off in your description of the caches. Each core has their own 128K L1 cache split (64K data / 64K code). Above that, each core has its own L2 cache which basically acts as a buffer between the L1 and L3 cache. Each socket has its own L3 ...


16

It is unlikely that these "minimum requirements" represent something below which the game will not run. Far more likely is that they represent something below which the game will not run with acceptable performance. No game company wants to deal with lots of customers complaining about crappy performance when they are running it on a single core 1 Ghz box, ...


15

Windows programs (winforms/WPF) should at all times stay responsive. With a naive implementation of a process that uses 100% cpu resources it's all too easy to make your program or even your system seem sluggish and hanging. With a good implementation (for instance: use a seperate thread with lower priority) it shouldn't be a problem. You shouldn't worry ...


15

There is generally nothing wrong with a program using 100% CPU while it is actually doing useful work and is not taking time away from anything more important. If a particular hardware platform is e.g. only capable of using 100% CPU continuously for one second before it has to throttle back to 50% to avoid overheating, it is generally better for an ...


13

we wanted it to be compiled so it’s not burning CPU doing the wrong stuff. Sounds like they are referring to compiled vs interpreted. Most likely down to the whole story of Twitter moving background processing tasks to Scala (compiled) after initially developing in Ruby On Rails (interpreted). An explanation of compiled vs interpreted code here. With a ...


13

Unsurprisingly, you are indeed "doomed from the start". This "Japanese Multiplication" (which is a visual form of the grid method tought in UK primary schools since the 1990s) has a time complexity of at least O(n^2) where n is the number of digits in the numbers you are multiplying. This is because the number of intersections will be n*n, and you have to ...


12

The lines of code have nothing to do with how the CPU executes it. I'd recommend reading up on assembler, because that will teach you a lot about how the hardware actually does things. You can also get assembler output from many compilers. That code might compile into something like (in a made up assembly language): load R1, [x] ; meaning load the data ...


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