Skip to main content
11 votes
Accepted

The difference between accumulator-based and register-based CPU architecture?

A register-based CPU architecture has one or more general purpose registers (where "general purpose register" excludes special purpose registers, like stack pointer and instruction pointer). An ...
Brendan's user avatar
  • 3,955
10 votes

How does a CPU load multiple bytes at once if memory is byte addressed?

Because the width of the data bus and the size of the smallest addressable unit are two separate things. Just because you can specify addresses at the byte level, does not mean you have to have an 8 ...
8bittree's user avatar
  • 5,656
8 votes

Why data alignment is used exactly?

Essentially, yes. It is possible for the CPU to read memory at non-aligned addresses, but it takes longer. This is probably a simplification, but it works something like this: There are generally a ...
user1118321's user avatar
  • 4,991
7 votes
Accepted

Why is the data for an x86 GDT entry designed this way?

Because the x86 architecture was originally 16-bit, it then evolved addendums as it had to address more and more memory, and work with larger and larger registers. The layout wasn't changed for ...
Kain0_0's user avatar
  • 16.2k
6 votes
Accepted

How to align on both word size and cache lines in x86

To understand how alignment affects things, let's look at a larger context. First, as you note, 2600 bytes of UTF-8 (or any kind of data) will indeed take 2600 bytes. If you allocate 2600 bytes from ...
Erik Eidt's user avatar
  • 34.2k
5 votes

How to align on both word size and cache lines in x86

It seems your confusion comes from mixing up some architectural levels. You have your processor architecture that may be 64 bits, making it "easy" to work on chunks that align with 64 bit boundaries. ...
Martin Maat's user avatar
  • 18.4k
5 votes

What is the difference between Times and Dup in Assembly Language?

DUP is a specific operand specifier to the DB/DW/etc psuedo-instructions, telling them to repeat a specific value. It can only be used in these data instructions. TIMES is a generic instruction ...
Jules's user avatar
  • 17.8k
4 votes

How does Branch Target Prediction differ from Branch Prediction?

Put simply: Branch Prediction predicts the answer to "Will I branch?" Branch Target Prediction predicts the answer to "Where will I branch to?" Both of these are considered at the same time. An ...
Alexander's user avatar
  • 4,954
4 votes

How does Branch Target Prediction differ from Branch Prediction?

Indirect jumps / calls (through a function pointer or a switch using a jump table) don't have the branch target available when an instruction is decoded. Even without a cache miss or something, jmp ...
Peter Cordes's user avatar
3 votes
Accepted

Registers and Stacks in NASM

Unlike with Java or C# I can't just use google as well, since Assembly just isn't used by many anymore. I don't think this is accurate: I found dozens of helpful articles and presentations by ...
Erik Eidt's user avatar
  • 34.2k
3 votes

How does a CPU load multiple bytes at once if memory is byte addressed?

As an example to illustrate the workings, let's first talk about a classic 32-bit processor like the good old 68020. For various reasons (compatibility, usability for ASCII characters, ...), even 32-...
Ralf Kleberhoff's user avatar
3 votes
Accepted

x86 lock instruction - simulator

So how treat lock prefix with 8086 alone. ignore it. How to treat lock prefix if exists other processors like FPU. Introduce a "Memory Lock" flag, visible by all hardware in the simulation ...
Mike Nakis's user avatar
  • 32.2k
3 votes

Testing a bootloader written from scratch?

There's a good getting-started tutorial here. In the tutorial they use QEMU, an x86 emulator. It's not a full-featured as VirtualBox, but if you're just testing a boot loader, it may be better as it's ...
TMN's user avatar
  • 11.4k
2 votes

Why (not) segmentation?

Segmentation leads to slower page translations and swapping For those reasons, segmentation was largely dropped on x86-64. The main difference between them is that: paging splits memory into fixed ...
Ciro Santilli OurBigBook.com's user avatar
2 votes

Make multithreaded program asynchronous

There is more than one way to add asynchronicity. You have explored one option, to make the single threaded application more asynchronous. Perhaps there is another option, to make a wrapper ...
Frank Hileman's user avatar
2 votes

How does x86 deal with register pairs?

It uses an internal temporary register. I pulled out my ancient copy of an original IBM 8086 Macro Assembler manual. The description of the XCHG instruction includes: The contents of the ...
1201ProgramAlarm's user avatar
2 votes

How does x86 deal with register pairs?

XCHG is a three micro-op instruction and takes more clock cycles than, say, a MOV. So right away we know it is doing something more complicated. If you check this post, the exchange could be ...
John Wu's user avatar
  • 26.6k
2 votes

How to align on both word size and cache lines in x86

The main point of alignment is to reduce the number of memory requests that are required for each operation. Processors typically fetch and write memory in cache line sized chunks, when talking to ...
Jules's user avatar
  • 17.8k
1 vote
Accepted

Where on the 64bit memory of a PC would one byte end up?

The answer depends on the endienness of the machine. You would have to look in the specification as to whether byte 0 is the lowest bits of a word or the highest bits of a word. For the most part, it ...
Cort Ammon's user avatar
  • 11.6k
1 vote

What is meant by /0 in AMD64 specification?

FF /0 Notation indicating that FF is the first byte of an opcode, and a subopcode in the ModR/M byte has a value of 0. Here, for example, the ADD, ADC, and AND instructions all use ...
Erik Eidt's user avatar
  • 34.2k
1 vote

What tasks does a memory barrier enforces other than preventing the re-ordering of instructions?

The definitive source is the Intel Optimization Reference Manual. Look at the various fence instructions in Chapter 7, and the discussion on multithreading in Chapter 9. From Chapter 7: "The MFENCE (...
Frank Hileman's user avatar
1 vote
Accepted

Intel Memory Addressing Form

I'm looking at the addressing mode table, and it says ~: [register1] + [register2*scale] + [displacement] Despite the usual meaning of []s, there is no way that the above means the memory contents ...
Erik Eidt's user avatar
  • 34.2k
1 vote

Make multithreaded program asynchronous

Depending on your setup and requirements, if queries are mostly reads and not much writes (such as a reporting system), you might be able to replicate the data to a database of your own which supports ...
William L's user avatar
  • 104
1 vote

The difference between accumulator-based and register-based CPU architecture?

Beyond the obvious difference of one register vs. many registers, a significant difference is in the way that operands are specified. An architecture with many registers may specify a binary operator ...
Erik Eidt's user avatar
  • 34.2k

Only top scored, non community-wiki answers of a minimum length are eligible