Timeline for Why is CPU cache memory so fast?
Current License: CC BY-SA 3.0
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| Apr 1, 2014 at 15:12 | history | edited | old_timer | CC BY-SA 3.0 |
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| Apr 1, 2014 at 10:34 | comment | added | Ruslan | @dwelch CMOS FETs don't drain power if they are in open or closed state, so the argument about power consumption is invalid. Moreover, it's the CMOS logic switching, which makes CPUs drain most of their power - the current peaks in the intermediate state (non-1 and non-0), so the situation is inverse to what you say :) | |
| Mar 31, 2014 at 23:43 | comment | added | MSalters | SRAM in caches generally is 6T, not 4T. Also, SRAM (certainly the 6T variant) is more energy efficient. The real power draw in DRAM is the refresh cycle, and SRAM just doesn't need that. SRAM transistors draw power when switching, the DRAM capacitor leaks all the time. If you replace the leaky cap of DRAM, you end up with EEPROM but that's not fast: if it's hard for the charge to leak out, it's also hard to get it out the normal way. | |
| Mar 31, 2014 at 17:05 | history | edited | old_timer | CC BY-SA 3.0 |
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| Mar 31, 2014 at 13:46 | comment | added | old_timer | agreed, more power, and slower relative to other sram. I think it is 4 transistors per bit for sram and 1 per bit for dram. dram relies on the capacitance in the fet, where sram relies on good old fashioned logic. so you have to power all of those transistors all the time and not just pump the charge periodically. | |
| S Mar 31, 2014 at 13:27 | history | suggested | user2428118 | CC BY-SA 3.0 |
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| Mar 31, 2014 at 13:01 | review | Suggested edits | |||
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| Mar 31, 2014 at 11:30 | comment | added | Darkhogg | Not to mention the fact that making SRAM bigger makes it WAY slower. | |
| Mar 31, 2014 at 7:28 | comment | added | 9000 | SRAM is also more power-hungry per bit, so you'd have to add radiators to it, and anything battery-powered would suffer. | |
| Mar 31, 2014 at 1:27 | history | answered | old_timer | CC BY-SA 3.0 |